參數(shù)資料
型號(hào)： pentium II cpu with mobile
廠商： Intel Corp.
英文描述： pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器)
中文描述： 奔騰II處理器芯片上緩存手機(jī)模塊連接器2（絲裂霉素2）（帶緩存和連接器2的奔二處理器）
文件頁(yè)數(shù)： 10/48頁(yè)
文件大?。?/td> 537K
代理商： PENTIUM II CPU WITH MOBILE
Intel
a
Pentium
a
II Processor With On-Die Cache Mobile Module MMC-2
10
3.1.3
AGP (60 Signals)
Table 3 lists the AGP interface signals.
Table 3. AGP Signal Descriptions
Name
Type
Voltage
Description
GAD[31:0]
I/O
AGP
V_3
AGP Address/Data
: The standard AGP address and data lines. This bus functions in
the same way as the PCI AD[31:0] bus. The address is driven with FRAME# assertion
and data is driven or received in following clocks.
GC/BE[3:0]#
I/O
AGP
V_3
AGP Command/Byte Enable
: This bus carries the command information during AGP
cycles when PIPE# is used. During an AGP write, this bus contains byte enable
information. The command is driven with FRAME# assertion and byte enables
corresponding to supplied or requested data are driven on the following clocks.
GFRAME#
I/O
AGP
V_3
AGP Frame
: Not used during AGP transactions. Remains deasserted by an internal
pullup resistor. Assertion indicates the address phase of a PCI transfer. Negation
indicates that the cycle initiator desires one more data transfer.
GDEVSEL#
I/O
AGP
V_3
AGP Device Select
: Same function as PCI DEVSEL#. It is not used during AGP
transactions. The 82433BX Host Bridge system controller drives this signal when a PCI
initiator is attempting to access DRAM. DEVSEL# is asserted at medium decode time.
GIRDY#
I/O
AGP
V_3
AGP Initiator Ready
: Indicates the AGP compliant target is ready to provide
all
write
data for the current transaction. Asserted when the initiator is ready for a data transfer.
GTRDY#
I/O
AGP
V_3
AGP Target Ready
: Indicates the AGP compliant master is ready to provide
all
write
data for the current transaction. Asserted when the target is ready for a data transfer.
GSTOP#
I/O
AGP
V_3
AGP Stop
: Same function as PCI STOP#. It is not used during AGP transactions.
Asserted by the target to request the master to stop the current transaction.
GREQ#
I
AGP
V_3
AGP Request
: AGP master requests for AGP.
GGNT#
O
AGP
V_3
AGP Grant
: Same function as on PCI. Additional information is provided on the ST[2:0]
bus. PCI Grant: Permission is given to the master to use PCI.
GPAR
I/O
AGP
V_3
AGP Parity
: A single parity bit is provided over GAD[31:0] and GC/BE[3:0]. This signal
is not used during AGP transactions.
PIPE#
I
AGP
V_3
Pipelined Request
: Asserted by the current master to indicate a full width address that
is to be queued by the target. The master queues one request each rising clock edge
while PIPE# is asserted.
SBA[7:0]
I
AGP
V_3
Sideband Address
: This bus provides an additional conduit to pass address and
commands to the 82433BX Host Bridge System Controller from the AGP master.
RBF#
I
AGP
V_3
Read Buffer Full
: Indicates if the master is ready to accept previously requested, low-
priority read data.
ST[2:0]
O
AGP
V_3
Status Bus
: Provides information from the arbiter to an AGP Master on what it may do.
These bits only have meaning when GGNT is asserted.
ADSTB[B:A]
I/O
AGP
V_3
AD Bus Strobes
: Provide timing for double-clocked data on the GAD bus. The agent
providing data drives these signals. These are identical copies of each other.
SBSTB
I
AGP
V_3
Sideband Strobe
: Provides timing for a sideband bus. The SBA[7:0] (AGP master)
drives the sideband strobe.
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