- 您現(xiàn)在的位置：買賣IC網 > PDF目錄369993 > pentium II cpu with mobile (Intel Corp.) pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器) PDF資料下載
參數(shù)資料
| 型號： | pentium II cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機模塊連接器2（絲裂霉素2）（帶緩存和連接器2的奔二處理器） |
| 文件頁數(shù)： | 28/48頁 |
| 文件大小： | 537K |
| 代理商： | PENTIUM II CPU WITH MOBILE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Intel
a
Pentium
a
II Processor With On-Die Cache Mobile Module MMC-2
28
4.6.2
AC Requirements
Table 18 shows the BCLK AC requirements.
Table 18. AC Specifications at the Processor Core Pins
1,2,3
Min
Nom
T#
PSB Frequency
4
Parameter
Max
Unit
Figure
Notes
66.67
MHz
All processor core
frequencies
T1:
BCLK Period
4, 5
BCLK Period Stability
6, 7, 8
15.0
ns
T2:
±250
ps
T3:
BCLK High Time
5.3
ns
At >1.8V
T4:
BCLK Low Time
BCLK Rise Time
8
BCLK Fall Time
8
5.3
ns
At <0.7V
T5:
0.175
0.875
ns
(0.9V-1.6V)
T6:
0.175
0.875
ns
(1.6V–0.9V)
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All GTL+ signal
timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All CMOS signal
timings (compatibility signals, etc.) are referenced at 1.25V at the processor core pins.
The internal core clock frequency is derived from the PSB clock. The PSB clock to core clock ratio is determined during initialization
as described and is predetermined by the Pentium II processor with on-die cache mobile module MMC-2.
The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the
CK97 Clock Synthesizer/Driver Specification
for further
information.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of BCLK skew
between devices.
The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock
driver. The -20 dB attenuation point, as measured into a 10-pF to a 20-pF load, should be less than 500 kHz. This specification may
be ensured by design characterization and/or measured with a spectrum analyzer. See the
CK97 Clock Synthesizer/Driver
Specification
for further details.
Not 100% tested. Specified by design characterization as a clock driver requirement.
3.
4.
5.
6.
7.
8.
相關PDF資料 |
PDF描述 |
|---|---|
| pentium II cpu | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復。