參數(shù)資料
型號(hào)： pentium II cpu with mobile
廠商： Intel Corp.
英文描述： pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器)
中文描述： 奔騰II處理器芯片上緩存手機(jī)模塊連接器2（絲裂霉素2）（帶緩存和連接器2的奔二處理器）
文件頁(yè)數(shù)： 17/48頁(yè)
文件大?。?/td> 537K
代理商： PENTIUM II CPU WITH MOBILE
Intel
a
Pentium
a
II Processor With On-Die Cache Mobile Module MMC-2
17
3.1.10
ITP and JTAG (9 Signals)
Table 10 lists the ITP and JTAG signals, which the system
manufacturer can use to implement a JTAG chain and an
ITP port if desired.
Table 10. ITP and JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUPU
JTAG Test Data Out:
Serial output port. TAP instructions and data are shifted out of the
processor from this port.
TDI
I
V_CPUPU
JTAG Test Data In:
Serial input port. TAP instructions and data are shifted into the
processor from this port.
TMS
I
V_CPUPU
JTAG Test Mode Select:
Controls the TAP controller change sequence.
TCLK
I
V_CPUPU
JTAG Test Clock:
Testability clock for clocking the JTAG boundary scan sequence.
TRST#
I
V_CPUPU
JTAG Test Reset:
Asynchronously resets the TAP controller in the processor.
FS_RESET#
O
GTL+
Processor Reset:
Processor reset status to the ITP.
VTT
O
V_CORE
GTL+ Termination Voltage:
Used by the POWERON pin on the ITP debug port to
determine when target system is on. POWERON pin is pulled up using a 1-K
resistor
to VTT.
FS_PREQ#
I
V_CPUPU
Debug Mode Request:
Driven by the ITP and makes request to enter debug mode.
FS_PRDY#
O
GTL+
Debug Mode Ready:
Driven by the processor and informs the ITP that the processor is
in debug mode.
NOTE:
DBREST# (reset target system) on the ITP debug port can be “l(fā)ogically ANDed” with VR_PWRGD TO PIIX4E/M’s PWROK.
3.1.11
Miscellaneous (82 Signals)
Table 11 lists the miscellaneous signal pins.
Table 11. Miscellaneous Pins
Name
Type
Number
Description
Module
ID[3:0]
O
CMOS
4
Module Revision ID
: These pins track the revision level of the Pentium II processor with
on-die cache mobile module MMC-2. A 100-K pullup resistor to V_3S must be placed on
the system electronics for these signals. See Section 7.0, “Labeling Information” for
more information.
Ground
I
45
Ground.
Reserved
RSVD
33
Unallocated Reserved pins and should not be connected.
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