
QuadFALC
TM
PEF 22554 E
Functional Description T1/J1
Data Sheet
194
Rev. 1.2, 2006-01-26
Note that an AIS-CI and an AIS signal (alarm indication signal) or a signal that is OOF (out of frame) will typically
cause an SEF defect.
For indication and clear condition see Table 59.
5.5.2
Automatic Modes (T1/J1))
In T1/J1 mode the following automatic modes are performed by the QuadFALC
TM:
Automatic remote alarm (Yellow Alarm) access: If the receiver has lost its synchronization (FRS0.LFA) a
remote alarm (yellow alarm) is sent to the distant end automatically, if enabled by bit FMR2.AXRA. In
synchronous state the remote alarm bit is removed.
Automatic AIS to system interface: In asynchronous state the synchronizer enforces an AIS to the receive
system interface automatically. However, received data is switched through transparently if bit FMR2.DAIS is
set.
Automatic clock source switching: In slave mode (LIM0.MAS = 0) the DCO-R synchronizes on the recovered
route clock. In case of loss-of-signal (LOS) the DCO-R switches to master mode automatically. If bit
CMR1.DCS is set, automatic switching from recovered route clock to SYNC is disabled, see also Table 16.
Automatic freeze signaling: Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is activated automatically, if a loss-of-signal or a loss of multiframe
alignment or a receive slip occurs. The internal signaling buffer RS(12:1) is frozen. Optionally automatic freeze
signaling is disabled by setting bit SIC3.DAF = 1.
Automatic local and remote loop switching based on In-Band loop codes, see Chapter 5.5.7.
Automatic payload and remote loop switching based on Out-Band loop codes, see Chapter 5.5.8.
5.5.3
Error Counter (T1/J1)
The QuadFALC
TM offers six error counters where each of them has a length of 16 bit. They record code violations,
framing bit errors, CRC6 bit errors, errored blocks and the number of received multiframes in asynchronous state
or the changes of frame alignment (COFA):
COFA event counter
PRBS Bit Error Counter (BEC)
CRC Error Counter (CEC)
Errored Block counter.
Code violation counter.
Counting of the counters can be disabled by appropriate bits in the register DEC (DEC_T).
Counting of the multiframes in asynchronous state and of the COFA parameter is done in a 6/2-bit counter. Each
of the error counters is buffered. Buffer update is done in two modes:
One-second accumulation
On demand using handshake with writing to the DEC register.
In the one-second mode an internal/external one-second timer updates these buffers and resets the counter to
accumulate the error events in the next one-second period. The error counter cannot overflow. Error events
occurring during error counter reset are not be lost.
5.5.3.1
Frame Error Counter FEC (T1/J1)
The kind of count up behaviour of the frame error counter FEC can be controlled in the QuadFALC
TM by the
register bit DEC.FECC (DEC_T) because there are differences in the ANSI standard T1- 403 between 1995 and
1999:
FEC count up will be done also if a severely error occurs as it is described in ANSI-T1-403 1995: DEC.FECC
= 0
B.
FEC count up is not done if a simultaneous severely error occurs as described in ANSI-T1-403 1999:
DEC.FECC = 1
B.
Note that the FEC status is stored in the registers FECH and FECL.