![](http://datasheet.mmic.net.cn/330000/PEB22554_datasheet_16444002/PEB22554_329.png)
Semiconductor Group
329
09.98
PEB 22554
Operational Description T1 / J1
Transmit Signaling Register (Write)
Value after RESET: not defined
Transmit Signaling Register 1-12
The transmit signaling register access is enabled by setting bit FMR5.EIBR = 1. Each
register contains the bit robbing information for 8 DS0 channels. With the transmit CAS
empty interrupt ISR1.CASE the contents of these registers will be copied into a shadow
register. The contents will subsequently sent out in the corresponding bit positions of the
next outgoing multiframe. XS1.7 will be sent out first in channel 1 frame 1 and XS12.0
will be sent out last. The transmit CAS empty interrupt ISR1.CASE requests that these
registers should be serviced within the next 3 ms. If requests for new information are
ignored, current contents will be repeated.
If access to XS1-12 registers is done without control of the interrupt ISR1.CASE and the
write access to these registers is done exact in that moment when this interrupt is
generated, data may be lost.
Note: A software reset (CMDR.XRES) will reset these registers.
7
0
XS1
A1
B1
C1/A2
D1/B2
A2/A3
B2/B3
C2/A4
D2/B4
(x70)
XS2
A3/A5
B3/B5
C3/A6
D3/B6
A4/A7
B4/B7
C4/A8
D4/B8
(x71)
XS3
A5/A9
B5/B9
C5/A10
D5/B10
A6/A11
B6/B11
C6/A12
D6/B12
(x72)
XS4
A7/A13
B7/B13
C7/A14
D7/B14
A8/A15
B8/B15
C8/A16
D8/B16
(x73)
XS5
A9/A17
B9/B17
C9/A18
D9/B18
A10/A19
B10/B19 C10/A20 D10/B20
(x74)
XS6
A11/A21 B11/B21 C11/A22 D11/B22 A12/A23
B12/B23 C12/A24 D12/B24
(x75)
XS7
A13/A1
B13/B1
C13/A2
D13/B2
A14/A3
B14/B3
C14/A4
D14/B4
(x76)
XS8
A15/A5
B15/B5
C15/A6
D15/B6
A16/A7
B16/B7
C16/A8
D16/B8
(x77)
XS9
A17/A9
B17/B9
C17/A10 D17/B10 A18/A11
B18/B11 C18/A12 D18/B12
(x78)
XS10
A19/A13 B19/B13 C19/A14 D19/B14 A20/A15
B20/B15 C20/A16 D20/B16
(x79)
XS11
A21/A17 B21/B17 C21/A18 D21/B18 A22/A19
B22/B19 C22/A20 D22/B20
(x7A)
XS12
A23/A21 B23/B21 C23/A22 D23/B22 A24/A23
B24/B23 C24/A24 D24/B24
(x7B)