![](http://datasheet.mmic.net.cn/330000/PEB22554_datasheet_16444002/PEB22554_295.png)
Semiconductor Group
295
09.98
PEB 22554
Operational Description T1 / J1
Framer Mode Register 0 (Read/Write)
Value after RESET: 00
H
XC1…XC0…
Transmit Code
Serial code transmitter is independent to the receiver.
00… NRZ (optical interface)
01… CMI (1T2B + B8ZS), (optical interface)
10… AMI coding with Zero Code Suppression (ZCS, B7 - Stuffing).
Disabling of the ZCS is done by activating the clear channel mode via
register CCB1-3. (ternary or digital interface)
11… B8ZS Code (ternary or digital dual rail interface)
RC1…RC0…
Receive Code
Serial code receiver is independent to the transmitter.
00… NRZ (optical interface)
01… CMI (1T2B + B8ZS), (optical interface)
10… AMI coding with Zero Code Suppression (ZCS, B7 - Stuffing),
(ternary or digital dual rail interface)
11… B8ZS Code (ternary or digital dual rail interface)
FRS…
Force Resynchronization
A transition from low to high will force the frame aligner to execute a
resynchronization of the pulse frame. In the asynchronous state, a
new frame position is assumed at the next candidate if there is one.
Otherwise, a new frame search with the meaning of a general reset is
started. In the synchronous state this bit will have the same meaning
as bit FMR0.EXLS except if FMR2.MCSP=1.
SRAF…
Select Remote (Yellow) Alarm Format for F12 and ESF Format
0…
F12: bit2 = 0 in every channel. ESF: pattern
‘1111 1111 0000 0000…’ in data link channel.
1…
F12: FS bit of frame 12. ESF: bit2 = 0 in every channel
EXLS…
External Loss Of Frame
With a low to high transition a new frame search will be started. This
has the meaning of a general reset of the internal frame alignment
unit. Synchronous state is reached only if there is one definite framing
candidate. In the case of multiple candidates, the setting of the bit
7
0
FMR0
XC1
XC0
RC1
RC0
FRS
SRAF
EXLS
SIM
(x1C)