
PEB 22554
Operational Description E1
Semiconductor Group
160
09.98
LLBDD…
Line Loop Back Deactuation Signal Detected
This bit is set to one in case the LLB deactuate signal is detected and
then received over a period of more than 25 msec with a bit error rate
less than 1/100. The bit remains set as long as the bit error rate does
not exceed 1/100.
If framing is aligned, the timeslot 0 is not taken into account for the
error rate calculation.
Any change of this bit will cause a LLBSC interrupt.
LLBAD…
Line Loop Back Actuation Signal Detected
Depending on bit LCR1.EPRM the source of this status bit changed.
LCR1.EPRM=0: This bit is set to one in case the LLB actuate signal
is detected and then received over a period of more than 25 msec with
a bit error rate less than 1/100. The bit remains set as long as the bit
error rate does not exceed 1/100.
If framing is aligned, the timeslot 0 is not taken into account for the
error rate calculation.
Any change of this bit will cause a LLBSC interrupt.
PRBS Status
LCR1.EPRM=1: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a BER 1/10. A data stream containing all
zeros with / without framing bits is also a valid pseudo random bit
sequence.
RSIF…
Receive Spare Bit for International Use (FAS Word)
First bit in FAS-word. Used only in doubleframe format, otherwise
fixed to ‘1’.
RS13…
Receive Spare Bit (Frame 13, CRC Multiframe)
First bit in service word of frame 13. Significant only in CRC-
multiframe format, otherwise fixed to ‘0’. This bit is updated with
beginning of every received CRC multiframe.
RS15…
Receive Spare Bit (Frame 15, CRC Multiframe)
First bit in service word of frame 15. Significant only in CRC-
multiframe format, otherwise fixed to ‘0’. This bit is updated with
beginning of every received CRC multiframe.