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| 型號(hào)： | OM6208 |
| 英文描述： | 65 x 96 pixels matrix grey-scale LCD driver |
| 中文描述： | 65 × 96像素矩陣灰度LCD驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 7/68頁 |
| 文件大?。?/td> | 296K |
| 代理商： | OM6208 |
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2003 feb 10
7
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
7
FUNCTIONAL DESCRIPTION
7.1
I/O buffers and interfaces
One of four industrial standard interfaces can be selected
using the interface configuration inputs PS1 and PS0.
Table 1
Serial/I
2
C-bus interface selection
7.2
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required
when the internal oscillator is used. An external clock
signal, if used, is connected to this input.
7.3
Address counter
The Address Counter (AC) assigns addresses to the
displaydata RAMforwriting. The X address X[6:0] andthe
Y address Y[4:0] are set separately.
7.4
Display data RAM
The OM6208 contains a 65
×
96
×
2 bit static RAM which
stores the display data. The display data RAM is divided
into 17 banks of 96 bytes, although only two bits of the
17th bank are used. During RAM access, data is
transferred to the RAM via the serial interface. There is a
direct correspondence between X address and column
output number.
7.5
Display address counter
The display is generated by simultaneously reading out
the RAM content for two or four rows, depending on the
current display size that is selected. This content will be
processed with the corresponding set of two or four
orthogonal functions and so generate the signals for
switching the pixels of the display on or off according to the
RAM content.
The display status (all dots on/all dots off and
normal/inverse video) is set by the bits DON, DAL and E
in the command Display control (see Table 8).
7.6
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
7.7
Data processing
The data processing block receives data from the RAM
and the orthogonal function from the logic circuits, then
selects the correct voltage level to be provided to the
columns.
7.8
High voltage generator
The high voltage generator provides the programmed
V
LCD
to the bias voltage generator block.
7.9
Bias voltage generator
The bias voltage generator generates all the voltage levels
required for the MRA driving system.
7.10
Command decoder
The command decoder identifies command words arriving
at the interface and routes the data bytes that follow to
their destination.
7.11
Orthogonal function generator
The orthogonal function generator generates a set of
orthogonal functions suitable for the selected value of p
(number of active rows).
7.12
Reset
The reset block handles the hardware reset input (RES)
and software reset and provides all internal blocks with the
required reset signal.
7.13
Row drivers and column drivers
The OM6208 contains 65 row and 96 column drivers
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. A typical MRA driving scheme with waveforms
for p = 4 is shown in Fig.2. The value of p represents the
number of simultaneously selected rows.
PS1
PS0
SELECTED INTERFACE
0
0
1
1
0
1
0
1
3-line SPI
4-line SPI
I
2
C-bus interface
3-line serial interface
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