參數(shù)資料
型號(hào)： OM6208
英文描述： 65 x 96 pixels matrix grey-scale LCD driver
中文描述： 65 × 96像素矩陣灰度LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 16/68頁(yè)
文件大?。?/td> 296K
代理商： OM6208
2003 feb 10
16
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
9.2
Serial interface (3-line)
The serial interface is also a 3-line bidirectional interface
for communication between the microcontroller and the
LCD driver chip. The three lines are SCE (chip enable),
SCLK(serialclock)andSDATA(serialdata).TheOM6208
is connected to the SDA of the microcontroller by the
SDATA(datainput) andSDO(dataoutput) padswhich are
connected together.
9.2.1
W
RITE MODE
The write mode of the interface means that the
microcontroller writes instructions and data to the
OM6208. Each data packet contains a control bit D/C and
a transmission byte. If D/C is LOW, the following byte is
interpreted as command byte. The instruction set is given
in Table 7. If D/C is HIGH, the following byte is stored in
the display data RAM. After every data byte the address
counter is incremented automatically. The general format
of the write mode and the definition of the transmission
byte is shown in Fig.15.
Any instruction can be sent in any order to the OM6208.
The MSB is transmitted first. The serial interface is
initialized when SCE is HIGH. In this state, SCLK clock
pulses have no effect and no power is consumed by the
serial interface. A falling edge on SCE enables the serial
interface and indicates the start of data transmission.
Figures 16, 17 and 18 show the protocol of the write
mode:
When SCE is HIGH, SCLK clocks are ignored. During
the HIGH time of SCE the serial interface is initialized
(see Fig.16)
At the falling SCE edge, SCLK must be LOW
(see Fig.32)
SDATA is sampled at the rising edge of SCLK
D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1) byte; it is sampled with the first
rising SCLK edge
If SCE stays LOW after the last bit of a command/data
byte, the serial interface is ready for the D/C bit of the
next byte at the next rising edge of SCLK (see Fig.17)
A reset pulse with RES interrupts the transmission. The
data being written into the RAM may be corrupted. The
registers are cleared. If SCE is LOW after the rising
edge of RES, the serial interface is ready to receive the
D/C bit of a command/data byte (see Fig.18).
handbook, full pagewidth
MGW713
transmission byte
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
transmission byte
(1)
D/C
transmission byte
D/C
D/C
transmission byte
D/C
Fig.15 Serial data stream, write mode.
(1) A transmission byte may be a command byte or a data byte.
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