
2003 feb 10
29
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
11.4
Reset function
After reset, the LCD driver is in Power-down mode, the
RAM is undefined and the internal registers have the
status shown in Table 8.
11.5
Power-down mode
In the Power-down mode:
All LCD outputs (row and column outputs) are at V
SS
(display off)
Bias generator and V
LCD
generator are switched off;
external V
LCD
supply can be applied or disconnected
Oscillator is off (an external clock is possible)
RAM contents are unchanged; RAM data can be written
V
LCD
is discharged to V
SS
.
Power-down mode is active when the display is off
(DON = 0) and all the pixels are on (DAL = 1).
11.6
Display Control
The bits DON, E and DAL select the display mode (see
Table 9).
11.6.1
H
ORIZONTAL MIRRORING
When the MX input is at logic 0, the display RAM is written
from left to right (X = 0 is on the left side).
When the MX input is set to 1, the display RAM is written
from right to left (X = 0 is on the right side).
The MX input value has an impact on the way the RAM is
written: if a horizontal mirroring of the display is desired,
the RAM must be rewritten after changing the MX pad
value.
11.6.2
V
ERTICAL MIRRORING
When the MY bit is set to logic 1, the display is mirrored
vertically.
A change of this bit has an immediate effect on the display,
it is not necessary to rewrite RAM for the effect to take
place.
11.7
Set Yaddress of RAM
Y[4:0] defines the Y address of the display RAM.
Table 12
Yaddress range
11.8
Set X address of RAM
The X address points to the columns. The range of X is
0 to 95.
11.9
Bias levels
TheOM6208isagrey-scaledriverabletoprovidedifferent
bias voltage levels for rows and columns. The row voltage
values are V
LCD
, V
SS
and V
C
, generated using the resistor
chain shown in Fig.28.
The five levels used to drive the columns are shown in
Fig.28. These are V
2L
, V
1L
, V
C
, V
1H
and V
2H
, all of which
depend on the value of alpha. Table 13 shows all possible
combinations of alpha settable by programming the
BS[2:0] bits.
Y4
Y3
Y2
Y1
Y0
DISPLAY RAM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
bank 8
bank 9
bank 10
bank 11
bank 12
bank 13
bank 14
bank 15
bank 16