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參數(shù)資料
| 型號： | OM6208 |
| 英文描述： | 65 x 96 pixels matrix grey-scale LCD driver |
| 中文描述： | 65 × 96像素矩陣灰度LCD驅(qū)動器 |
| 文件頁數(shù)： | 19/68頁 |
| 文件大?。?/td> | 296K |
| 代理商： | OM6208 |
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2003 feb 10
19
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
10 I
2
C-BUS INTERFACE
10.1
Characteristics of the I
2
C-bus (Hs-mode)
The I
2
C-bus Hs-mode is for bidirectional, two-line
communication between different ICs or modules with
speeds up to 3.4 MHz. The only difference between
Hs-mode slave devices and F/S-mode slave devices is the
speed at which they operate, therefore the buffers on the
SDAH output have an open drain. This is the same for
I
2
C-bus master devices which have an open-drain SDAH
output and a combination of an open-drain pull-down and
current source pull-up circuits on the SCLH output. Only
the current source of one master is enabled at any one
time and only during Hs-mode. Both lines must be
connected to a positive supply via a pull-up resistor.
Data transfer may be initiated only when the bus is not
busy.
10.1.1
S
YSTEM CONFIGURATION
Definition (see Fig.20):
Transmitter: the device that sends the data to the bus
Receiver: the device that receives the data from the bus
Master: the device that initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronisation: procedure to synchronize the clock
signals of two or more devices.
MGA807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig.20 System configuration.
10.1.2
B
IT TRANSFER
One data bit is transferred during each clock pulse (see
Fig.21). The data on the SDAH line must remain stable
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as a control
signal.
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.21 Bit transfer.
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