參數(shù)資料
型號(hào): OM6208
英文描述: 65 x 96 pixels matrix grey-scale LCD driver
中文描述: 65 × 96像素矩陣灰度LCD驅(qū)動(dòng)器
文件頁(yè)數(shù): 18/68頁(yè)
文件大?。?/td> 296K
代理商: OM6208
2003 feb 10
18
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
9.2.2
R
EAD MODE
handbook, full pagewidth
MCE176
SCLK
SDATA
SDO
DB7
D/C
DB6
DB5
DB4
DB7 DB6 DB5 DB4
DB3 DB2 DB1
DB0
DB3
DB2
DB1 DB0
D/C
Fig.19 Read mode serial interface 3-line.
The read mode of the interface means that the
microcontroller reads data from the OM6208. To do so the
microcontroller first has to send a command, the read
statuscommand,andthenthefollowingbyteistransmitted
in the opposite direction using SDO (see Fig.19). After
that, SCE is required to go HIGH before a new command
is sent.
The OM6208 samples the SDATA data at rising SCLK
edges and shifts SDO data at falling SCLK edges. Thus
the SDO data is available for the microcontroller to read at
rising SCLK edges.
After the read status command has been sent, the SDATA
line must be set to 3-state not later then at the falling SCLK
edge of the last bit (see Fig.19).
The 8th read bit is shorter than the others because it is
terminated by the rising SCLK edge (see Fig.35). The last
rising SCLK edge sets SDO to 3-state after the delay
time t
4
.
9.2.3
R
EAD DATA FORMAT
Regardless of which serial interface is used there are five
bits that can be read (ID1 to ID4 and VM) and one
temperatureregister.Forthebits,onebitistransmittedper
byte read and is selected by issuing the appropriate read
instruction from the instruction set. Bits ID1 and ID2 are
hard-wired so that ID1 always returns a logic 0 and ID2
always returns a logic 1. Bits ID3 and ID4 are the
identification bits and are set via ID3/SA0 and ID4/SA1
pads. The format for the read bit, B, is shown in Table 2.
Table 2
Read data format
Note
1.
x = undefined.
Table 3
Sending the instruction to read back the temperature sensor data will select the following status byte.
Read temperature sensor
Note
1.
x = undefined.
D7 (MSB)
x
(1)
D6
D5
D4
D3
D2
D1
D0 (LSB)
B
B
B
B
B
B
B
D7 (MSB)
x
(1)
D6
D5
D4
D3
D2
D1
D0 (LSB)
TD[6]
TD[5]
TD[4]
TD[3]
TD[2]
TD[1]
TD[0]
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