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參數(shù)資料
| 型號： | OM6208 |
| 英文描述： | 65 x 96 pixels matrix grey-scale LCD driver |
| 中文描述： | 65 × 96像素矩陣灰度LCD驅(qū)動器 |
| 文件頁數(shù)： | 27/68頁 |
| 文件大?。?/td> | 296K |
| 代理商： | OM6208 |
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2003 feb 10
27
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
11.1
Description of command bits
Table 8
Bit descriptions
Notes
1.
Calibration mode may not be entered if the SEAL bit has been set. Programming is only possible when in calibration
mode.
These values can be set by the module maker. If the factory defaults OTP bit (MMFD) has been set then these values
cannot be changed via the interface. Otherwise, the OTP data will only be used if bit SFD is set to 1.
FR[2:0] = 001 and T[2:0] = 110 gives 150 Hz as default frame frequency.
2.
3.
BIT
0
1
RESET STATE
DON
E
DAL
MY
PC
DOR
V
BRS
EC
CALMM
TCE
OSE
SFD
MOD
SLA[2:0]
SLB[2:0]
SLC[2:0]
SLD[2:0]
X[6:0]
Y[4:0]
S[1:0]
NL[6:0]
FR[2:0]
T[2:0]
D[7:0]
VPR[7:0]
BS[2:0]
FI
display off
normal display
normal display
no Y mirroring
charge pump off
normal data order
horizontal addressing
bottom rows are not mirrored
internal oscillator is selected
exit OTP calibration mode
disable temperature compensation
disable OTP programmed voltage
use interface programmed data
grey-scale mode is selected
display on
inverse video mode
all pixel on
Y mirroring
charge pump on
MSB/LSB transposed for RAM data
vertical addressing
bottom rows are mirrored
external clock to be used
enter OTP calibration mode
(1)
enable temperature compensation
enable OTP programmed voltage
(1)
use OTP programmed data
(2)
black-and-white mode is selected
select slope for segment A
select slope for segment B
select slope for segment C
select slope for segment D
sets X address (column) for writing in the RAM
sets Yaddress (bank) for writing in the RAM
charge pump multiplication factor (see Table 10)
sets N-line inversion (see Table 18)
sets frame frequency range (see Table 11)
oscillator tune; sets frame frequency within a range (see Table 11)
display data length for 3-line SPI interface
V
PR
register
bias setting level (see Table 13)
super-frame inversion
0
0
1
0
0
0
0
0
0
0
1
0
0
0
000
(2)
000
(2)
000
(2)
000
(2)
0000000
00000
0000
(2)
0001101
(2)
001
(2)(3)
110
(2)(3)
00000000
00000000
(2)
000
(2)
0
(2)
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