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參數(shù)資料
| 型號： | OM6208 |
| 英文描述： | 65 x 96 pixels matrix grey-scale LCD driver |
| 中文描述： | 65 × 96像素矩陣灰度LCD驅動器 |
| 文件頁數(shù)： | 28/68頁 |
| 文件大?。?/td> | 296K |
| 代理商： | OM6208 |
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2003 feb 10
28
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
Table 9
Display and power mode bits DON, DAL and E
Notes
1.
2.
3.
The DAL bit has priority over the E bit.
Refer also to Table 17.
X = don’t care.
Table 10
Multiplication settings for charge pump
11.2
Frame frequency setting and oscillator tuning
Grey-scale mode and black-and-white mode require
different frame frequencies. The appropriate frame
frequency (f
frame
) is derived from the oscillator frequency
(f
osc
) using a presettable divider as shown in the equation
There are eight possible divider settings and these are
selected by the parameter FR[2:0], see Table 11.
Table 11
Frame frequencies for f
osc
= 400 kHz
Oscillator tuning is controlled by the parameter T[2:0]. As
a result of oscillator tuning, f
OSC
is increased by
approximately 4% per step according to the equation
(1)
where T is the decimal value of T[2:0].
Example.
For the default values given in Table 8
(i.e. FR[2:0] = 001 and T[2:0] = 110) the selected frame
frequency is 122.5 Hz
×
(1 + 6
×
0.04) = 151.9 Hz.
Equation (1) shows the typical value of the oscillator
frequency. The accuracy of this parameter is defined in
Chapter 15. The frame frequency accuracy results directly
from the oscillator accuracy.
11.3
Initialization
Immediately following power-on, all internal registers and
the RAM content are undefined. A reset pulse must be
applied to the RES pad.
Reset is accomplished by applying an external reset pulse
(active LOW) to the RES input. When reset occurs within
the specified time, all internal registers are reset, however
the RAM remains undefined. The state after reset is
described in Section 11.4.
At power-on, the RES input must be
≤
0.3V
DD1
when V
DD1
reachesV
DD(min)
(orhigher)withinthemaximumtimet
VHRL
after V
DD1
going HIGH (see Fig.37). Alternatively a reset
pulse can be applied when V
DD1
is stable.
A reset can also be made by sending a reset command.
This command can be used during normal operation but
not to initialize the chip after power-on.
After power-off, the RES input must not be HIGH when
V
DD1
is not HIGH.
DON
DAL
(1)
E
(2)
X
(3)
DESCRIPTION
0
0
display off; all row and column
outputs at V
SS
; oscillator on;
HV generator enabled
Power-downmode;displayoff;
all row and column outputs at
V
SS
; oscillator off;
HV generator disabled
normal display mode
inverse display mode
all pixels on
0
1
X
(3)
1
1
1
0
0
1
0
1
X
(3)
S1
S0
VOLTAGE
MULTIPLIER
4
×
5
×
6
×
7
×
0
0
1
1
0
1
0
1
f
frame
f
division ratio
--------------------------------
=
FR2
FR1
FR0
DIVISION
RATIO
f
frame
(Hz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2448
3265
4082
4896
5714
7340
8968
11428
163.4
122.5
98.0
81.7
70.0
54.5
44.6
35.0
f
OSC
400 kHz
1
0.04
T
×
+
(
)
×
=
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