參數(shù)資料
型號(hào)： OM6208
英文描述： 65 x 96 pixels matrix grey-scale LCD driver
中文描述： 65 × 96像素矩陣灰度LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 21/68頁(yè)
文件大?。?/td> 296K
代理商： OM6208
2003 feb 10
21
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
10.2
I
2
C-bus Hs-mode protocol
The OM6208 is a slave receiver/transmitter. If data is to be
read from the device the SDAHOUT and SDAH pads must
be connected for acknowledge to be used (see Table 1,
note 6).
Hs-mode can only commence after the following
conditions.
START condition (S)
8-bit master code (00001XXX)
not-acknowledge bit (A).
The master code has two functions as shown in Figs 24
and 25, it allows arbitration and synchronization between
competing masters at F/S-mode speeds, resulting in one
winner. Also the master code indicates the beginning of an
Hs-mode transfer.
As no device is allowed to acknowledge the master code,
then a master code transmission must be followed by a
not-acknowledge (A). After this A bit, and the SCLH line
has been pulled up to a HIGH level, the active master
switches to Hs-mode and enables at t
H
the current-source
pull-up circuit for the SCLH signal (see Fig.25).
The active master will then send a repeated START
condition (Sr) followed by a 7-bit slave address with a
R/W bit, and receives an acknowledge bit (A) from the
selected slave. After each acknowledge bit (A) or
not-acknowledge bit (A) the active master disables its
current-source pull-up circuit. The active master
re-enables its current source again when all devices have
released and the SCLH signal reaches a HIGH level. The
rising of the SCLH is done by a resistor pull-up and so is
slower, the last part of the SCLH rise time is speeded up
because the current source is enabled. Data transfer only
switches back to F/S-mode after a STOP (P) condition.
The write sequence that occurs after the Hs-mode is
a START (S) condition from the I
2
C-bus master which is
followed by the slave address. All slaves with the
corresponding address acknowledge in parallel, all the
others will ignore the I
2
C-bus transfer.
After an acknowledgement cycle of a write (W), one or
more command words follow which define the status of the
addressed slaves. A command word consists of a control
byte, which defines Co and D/C, plus a data byte (see
Fig.26 and Table 4).
The last control byte is tagged with a cleared most
significantbit,thecontinuationbit Co.Thecontrolanddata
bytes are also acknowledged by all addressed slaves on
the bus.
Table 4
Co and Sr definition
Co
D/C
R/W
ACTION
0
last control byte to be sent; only a stream of data bytes are allowed to follow; this stream
may only be terminated by a STOP or repeated START condition
another control byte will follow the data byte unless a STOP or repeated START condition
is received
data byte will be decoded and used to set up the device
data byte will return the status byte
data byte will be stored in the display RAM
RAM read back is not supported
1
0
0
1
0
1
1
Afterthelastcontrolbyte,dependingontheD/Cbitsetting,
a series of display data bytes or command data bytes may
follow. If the Sr bit was set to logic 1, these display bytes
are stored in the display RAM at the address specified by
the data pointer. The data pointer is automatically updated
and the data is directed to the intended OM6208 device.
If the Sr bit of the last control byte was set to logic 0, these
command bytes will be decoded and the setting of the
device will be changed according to the received
commands. The acknowledgement after each byte is
made only by the addressed OM6208. At the end of the
transmission the I
2
C-bus master issues a STOP
condition (P) and switches back to F/S-mode, however, to
reduce the overhead of the master code, it i s possible that
a master links a number of Hs-mode transfers, separated
by repeated START conditions (Sr).
A read sequence (see Fig.27) follows after the Hs-mode is
selected. The OM6208 will immediately start to output the
requested data until a not acknowledge is transmitted by
the master. The write access should be terminated by a
repeated START condition so that the Hs-mode is not
disabled.
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