參數(shù)資料
型號(hào)： OM6208
英文描述： 65 x 96 pixels matrix grey-scale LCD driver
中文描述： 65 × 96像素矩陣灰度LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 25/68頁(yè)
文件大?。?/td> 296K
代理商： OM6208
2003 feb 10
25
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
11 INSTRUCTIONS
The OM6208 may be interfaced via 3-line or 4-line Serial
PeripheralInterface (SPI),3-lineserialinterfaceorI
2
C-bus
interface. In all cases, processing of instructions is
asynchronous and does not require the internal/external
oscillator to be running.
Data transmission to OM6208 may be of two types, those
that define the operating mode of the device (commands)
and those that fill display RAM (data). Table 7 lists all
commands that are recognised by OM6208.
The Most Significant Bit (MSB) is sent first. The mode in
which the D/C bit is defined varies with the type of serial
interface that is used.
D/C bit definitions:
With 4-line SPI interface selected, the D/C bit is
implemented as hard-wired input at pad D/C
With 3-line SPI interface selected, the D/C bit is not
implemented and all transmission are commands by
default unless preceded by the Display data length
command
With3-lineserialandI
2
C-businterfaceselected,theD/C
bit is implemented through the interface protocol.
Commands can consist of one byte (single-byte) and two
bytes (double-byte). Unless otherwise specified,
commands may be executed in any order.
Table 7
Instructions not expressly defined in this table and reserved instructions must not be used.
Instruction set
COMMAND NAME
D/C
COMMAND BYTE
FUNCTION DESCRIPTION
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
Write data
Horizontal addressing
Horizontal addressing
Power control
Charge pump control
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
7
0
0
0
0
δ
(1)
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
D
6
0
0
0
0
δ
(1)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D
5
0
0
1
1
δ
(1)
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
D
4
0
1
0
1
δ
(1)
0
V
pr4
1
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
D
3
X
3
δ
(1)
1
1
δ
(1)
0
V
pr3
0
0
0
1
1
1
Y
3
1
MY
1
1
1
1
1
1
0
D
2
X
2
X
6
PC
1
δ
(1)
V
pr7
V
pr2
BS
2
1
1
1
0
0
Y
2
1
δ
(1)
0
0
1
1
1
1
0
D
1
X
1
X
5
δ
(1)
0
S
1
V
pr6
V
pr1
BS
1
0
1
1
0
1
Y
1
1
δ
(1)
1
1
0
0
1
1
0
D
0
X
0
X
4
δ
(1)
1
S
0
V
pr5
V
pr0
BS
0
DAL
E
DON
DOR
V
Y
0
Y
4
δ
(1)
0
1
0
1
0
1
BRS
RAM data
set X address; lower 4 bits
set X address; upper 3 bits
charge pump on/off
set multiplication factor
Set V
PR
Set V
PR
Set bias
Display mode
Display mode
Display mode
Data order
RAM addressing
Vertical addressing
Vertical addressing
Vertical mirroring
ID read
ID read
ID read
ID read
Temperature sense
VM read
Row control
write V
pr
register
write V
pr
register
set bias
all on/normal display
normal/inverse display
display ON/OFF
swap RAM MSB/LSB order
vertical or horizontal mode
set Yaddress
set Yaddress
mirror Y
identification: ID1
(2)(3)
identification: ID2
(2)(3)
identification: ID3
(2)
identification: ID4
(2)
temperature read back
voltage monitor
(3)(4)
swap the bottom rows
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