- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363665 > NS32FX16-20 (National Semiconductor Corporation) Imaging/Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | NS32FX16-20 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號(hào)處理器 |
| 文件頁數(shù)： | 9/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
2.0 Architectural Description
(Continued)
I
If I
e
1, then all interrupts will be accepted. If I
e
0, only
the NMI interrupt is accepted. Trap enables are not af-
fected by this bit.
B
Reserved for use by the CPU. This bit is set to 1 during
the execution of the EXTBLT instruction and causes the
BPU signal to become active. Upon reset, B is set to
zero and the BPU signal is set high.
Note 1:
When an interrupt is acknowledged, the B, I, P, S and U bits are set
to zero and the BPU signal is set high. A return from interrupt will
restore the original values from the copy of the PSR register saved
in the interrupt stack.
Note 2:
If BITBLT (BB) or EXTBLT instructions are executed in an interrupt
routine, the PSR bits J and K must be cleared first.
2.1.4 Configuration Register
The Configuration Register (CFG) is 8 bits wide, of which
four bits are implemented. The implemented bits are used to
declare the presence of certain external devices and to se-
lect the clock scaling factor. CFG is programmed by the
SETCFG instruction. The format of CFG is shown in Figure
2-3. The various control bits are described below.
7
0
C
M
F
I
FIGURE 2-3. Configuration Register (CFG)
I
Interrupt vectoring. This bit controls whether maskable
interrupts are handled in nonvectored (I
e
0) or vectored
(I
e
1) mode. Refer to Section 3.2.3 for more information.
Floating-point instruction set. This bit indicates whether
a floating-point unit (FPU) is present to execute floating-
point instructions. If this bit is 0 when the CPU executes
a floating-point instruction, a Trap (UND) occurs. If this
bit is 1, then the CPU transfers the instruction and any
necessary operands to the FPU using the slave-proces-
sor protocol described in Section 3.1.3.1.
F
M
Clock scaling. This bit is used in conjuction with the C bit
to select the clock scaling factor.
C
Clock scaling. Same as the M bit above. Refer to Sec-
tion 3.5.3 on ‘‘Power Save Mode’’ for details.
2.1.5 DSP Module Registers
The DSP Module (DSPM) contains 6 memory-mapped reg-
isters. All the registers, except ST, are readable and writa-
ble. ST is read-only.
Accesses to these registers must be aligned; word and dou-
ble-word accesses must occur on word and double-word
address boundaries respectively. Section 2.2. Failing to do
so will cause unpredictable results. Figure 2-4 shows the
address map of the DSP Module Registers.
Register Names
Register
Addresses
A
FFFFD400
Y
FFFFD404
0
DPTR
FFFFD408
CPTR
FFFFD40C
CTL
FFFFD40E
ST
FFFFD410
FIGURE 2-4. DSP Module Registers Address Map
ADAccumulator.
This 32-bit register holds one complex
number, and is mapped into two consecutive 16-bit words,
called A0 and A1.
Internally, A0 and A1 are 32-bit registers, however, only bits
15–30 (16 bits) are accessible. The rest of the bits are used
for bigger dynamic range during intermediate calculations.
Section 3.4.
YDMultiplier Input Register.
This 32-bit register holds one
complex operand. The Y register is mapped into two con-
secutive words called Y0 and Y1.
DPTRDData Pointer.
24-bit pointer pointing at the data
vector in main memory. In order to implement circular buff-
ers, only the least significant bits of DPTR are incremented.
When the end of a buffer is reached, the least significant
bits of DPTR are reloaded with zeros. The number of bits
that are set to zero (which defines the size of the circular
buffer) is controlled by the CTL register. The least-signifi-
cant 16-bit word of DPTR is called DPTR0, and the most-
significant byte is called DPTR1. Bits 24–31 are reserved
and should be set to 0.
CPTRDCoefficient Memory Vector Pointer.
This 16-bit
register holds the address and length of the coefficient vec-
tor, stored in the on-chip RAM array. The format of CPTR is
shown in Figure 2–5.
15 14
8
7
6
0
0
LNGT
0
STRT
FIGURE 2-5. CPTR Register Format
STRT
Coefficient’s Vector Index. At the beginning of the
DSP operation, STRT points to the first coefficient in
the coefficient vector. Section 2.1.6.
LNGT
Coefficient’s Vector Length. This field specifies the
number of coefficients in the coefficient vector.
STRT and LNGT must be in the ranges 0 to 95 and 1 to 96
respectively. The relation LNGT
a
STRT
k
97 must also be
satisfied. Specifying values violating any of these conditions
will cause unpredictable results.
CTL Control Register.
This register controls the modes of
operation of the DSP Module. The format of CTL is shown in
Figure 2-6. The reserved bits should be set to 0. See Sec-
tion 3.4 for more details.
7
6 5
4 3
2 1
0
OPC
DS
RES
OPM
FIGURE 2-6. CTL Register Format
OPM
Opcode Modifier. This field is used to further qualify
the operation specified by OPC. See Section 3.4.3 for
details.
DS
Data Buffer Size. Specifies the number of complex
variables (4 bytes each) in the data buffer in main
memory.
DS
e
00
x
8 Complex Variables
DS
e
01
x
16 Complex Variables
DS
e
10
x
32 Complex Variables
DS
e
11
x
64 Complex Variables
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32FX16-25 | Imaging/Signal Processor |
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。