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| 型號： | NS32FX16-20 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號處理器 |
| 文件頁數(shù)： | 57/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-20 |
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3.0 Functional Description
(Continued)
3.5.5.10 Instruction Status
In addition to the four bits of Bus Cycle status (ST0–3), the
NS32FX16 CPU also presents Instruction Status informa-
tion on three separate pins. These pins differ from
ST0–3 in that they are synchronous to the CPU’s internal
instruction execution section rather than to its bus interface
section.
PFS (Program Flow Status) is pulsed low as each instruction
begins execution. It is intended for debugging purposes.
U/S originates from the U-bit of the Processor Status Regis-
ter, and indicates whether the CPU is currently running in
User or Supervisor mode. Although it is not synchronous to
bus cycles, there are guarantees on its validity during any
given bus cycle. See the Timing Specifications in Section 4.
ILO (Interlocked Operation) is activated during an SBITI (Set
Bit, Interlocked) or CBITI (Clear Bit, Interlocked) instruction.
It is made available to external bus arbitration circuitry in
order to allow these instructions to implement the sema-
phore primitive operations for multi-processor communica-
tion and resource sharing. ILO is guaranteed to be active
during the operand accesses performed by the interlocked
instructions.
Note:
The acknowledge of HOLD is on a cycle by cycle basis. Therefore, it
is possible to have HLDA active when an interlock operation is in
progress. In this case, ILO remains low and the interlocked instruction
continues only after HOLD is de-asserted.
4.0 Device Specifications
4.1 NS32FX16 PIN DESCRIPTIONS
The following is a brief description of all NS32FX16 pins.
The descriptions reference portions of the Function De-
scription, Section 3.
Unless otherwise indicated, reserved pins should be left
open.
Note:
An asterisk next to the signal name indicates a TRI-STATE condition
for that signal during HOLD acknowledge.
4.1.1 Supplies
V
CC
Power.
a
5V positive supply.
Ground.
GND
Ground reference for both on-chip logic and
output drivers.
4.1.2 Input Signals
RSTI
Reset Input.
Schmitt triggered, asynchronous signal used to
generate a CPU reset. See Section 3.5.4.
Note:
The reset signal is a true asynchronous input. Therefore,
no external synchronizing circuit is needed.
HOLD
Hold Request.
When active, causes the CPU to release the bus
for DMA or multiprocessing purposes. See Sec-
tion 3.5.5.9.
Note:
If the HOLD signal is generated asynchronously, its set
up and hold times may be violated. In this case, it is
recommended to synchronize it with CTTL to minimize
the possibility of metastable states.
The CPU provides only one synchronization stage to
minimize the HLDA latency. This is to avoid speed deg-
radations in cases of heavy HOLD activity (i.e., DMA
controller cycles interleaved with CPU cycles).
INT
Interrupt.
A low level on this pin requests a maskable inter-
rupt. INT must be kept asserted until the interrupt
is acknowledged.
NMI
Non-Maskable Interrupt.
A High-to-Low transition on this signal requests a
non-maskable interrupt.
Note:
INT and NMI are true asynchronous inputs. Therefore,
no external synchronizing circuit is needed.
CWAIT
Continuous Wait.
Causes the CPU to insert continuous wait states
if sampled low at the end of T2 and each follow-
ing T-State. See Section 3.5.5.3.
WAIT1–2 Two-Bit Wait State Inputs
These inputs, collectively called WAIT1–2, allow
from zero to three wait states to be specified.
They are binary weighted. See Section 3.5.5.3.
Note:
During a DMA cycle, WAIT1–2 should be kept inactive
unless they are also monitored by the DMA Controller.
Wait states, in this case, should be generated through
CWAIT.
OSCIN
Crystal/External Clock Input.
Input from a crystal or an external clock source.
See Section 3.5.2.
4.1.3 Output Signals
A16–A23
*
High-Order Address Bits.
These are the most significant 8 bits of the mem-
ory address bus.
*
High Byte Enable.
Status signal used to enable data transfers on
the most significant byte of the data bus.
HBE
ST0–3
Status.
Bus cycle status code; ST0 is the least signifi-
cant. Encodings are:
0000D Idle: CPU Inactive on Bus.
0001D Idle: WAIT Instruction.
0010D DSP Module Data Transfer.
0011D Idle: Waiting for Slave.
0100D Interrupt Acknowledge, Master.
0101D Interrupt Acknowledge, Cascaded.
0110D End of Interrupt, Master.
0111D End of Interrupt, Cascaded.
1000D Sequential Instruction Fetch.
1001D Non-Sequential Instruction Fetch.
1010D Data Transfer.
1011D Read Read-Modify-Write Operand.
57
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| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
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