- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363665 > NS32FX16-20 (National Semiconductor Corporation) Imaging/Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | NS32FX16-20 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號(hào)處理器 |
| 文件頁數(shù)： | 25/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
2.0 Architectural Description
(Continued)
2.5.3.3.1 Magnifying Compressed Data
Restoring data is just one application of the SBITS and
SBITPS instructions. Multiplying the ‘‘length’’ operand used
by the SBITS and SBITPS instructions causes the resulting
pattern to be wider, or a multiple of ‘‘length’’.
As the pattern of data is expanded, it can be magnified by
2x, 3x, 4x, . . . , 10x and so on. This creates several sizes of
the same style of character, or changes the size of a logo. A
magnify in both dimensions X and Y can be accomplished
by drawing a single line, then using the MOVS (Move String)
or the BB instructions to duplicate the line, maintaining an
equal aspect ratio.
More information on this subject is provided in the
NS32CG16 Printer/Display Processor Programmer’s Refer-
ence Supplement.
3.0 Functional Description
This chapter provides details on the functional characteris-
tics of the NS32FX16 microprocessor.
The chapter is divided into five main sections:
Instruction Execution, Exception Processing, Debugging,
DSP Module and System Interface.
3.1 INSTRUCTION EXECUTION
To execute an instruction, the NS32FX16 performs the fol-
lowing operations:
#
Fetch the Instruction
#
Read Source Operands, if Any (1)
#
Calculate Results
#
Write Result Operands, if Any
#
Modify Flags, if Necessary
#
Update the Program Counter
Under most circumstances, the CPU can be conceived to
execute instructions by completing the operations above in
strict sequence for one instruction and then beginning the
sequence of operations for the next instruction. However,
due to the internal instruction pipelining, as well as the oc-
currence of exceptions, the sequence of operations per-
formed during the execution of an instruction may be al-
tered. Furthermore, exceptions also break the sequentiality
of the instructions executed by the CPU.
Note 1:
In this and following sections, memory locations read by the CPU to
calculate effective addresses for Memory-Relative and External ad-
dressing modes are considered like source operands, even if the
effective address is being calculated for an operand with access
class of write.
3.1.1 Operating States
The CPU has four operating states regarding the execution
of instructions and the processing of exceptions: Reset, Ex-
ecuting Instructions, Processing An Exception and Waiting-
For-An-Interrupt. The various states and transitions be-
tween them are shown in Figure 3-1.
Whenever the RSTI signal is asserted, the CPU enters the
reset state. The CPU remains in the reset state until the
RSTI signal is driven inactive, at which time it enters the
Executing-Instructions state. In the Reset state the contents
of certain registers are initialized. Refer to Section 3.5.4 for
details.
TL/EE/10818–10
FIGURE 3-1. Operating States
In the Executing-Instructions state, the CPU executes in-
structions. It will exit this state when an exception is recog-
nized or a WAIT instruction is encountered. At which time it
enters the Processing-An-Exception state or the Waiting-
For-An-Interrupt state respectively.
While in the Processing-An-Exception state, the CPU saves
the PC, PSR and MOD register contents on the stack and
reads the new PC and module linkage information to begin
execution of the exception service procedure.
Following the completion of all data references required to
process an exception, the CPU enters the Executing-In-
structions state.
In the Waiting-For-An-Interrupt state, the CPU is idle. A spe-
cial status identifying this state is presented on the system
interface (Section 3.5). When an interrupt is detected, the
CPU enters the Processing-An-Exception State.
3.1.2 Instruction Endings
The NS32FX16 checks for exceptions at various points
while executing instructions. Certain exceptions, like inter-
rupts, are in most cases recognized between instructions.
Other exceptions, like Divide-By-Zero Trap, are recognized
during execution of an instruction. When an exception is
recognized during execution of an instruction, the instruction
ends in one of four possible ways: completed, suspended,
terminated, or partially completed. Each type of exception
causes a particular ending, as specified in Section 3.2.
25
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32FX16-25 | Imaging/Signal Processor |
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。