- 您現(xiàn)在的位置：買賣IC網 > PDF目錄363665 > NS32FX16-20 (National Semiconductor Corporation) Imaging/Signal Processor PDF資料下載
參數資料
| 型號： | NS32FX16-20 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號處理器 |
| 文件頁數： | 51/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
3.0 Functional Description
(Continued)
Write cycle, the CPU applies data and activates SPC at T1,
removing SPC at T4. The Slave Processor latches the
status on the leading edge of SPC and latches data on the
trailing edge.
The CPU does not pulse the Address Strobe (ADS), and no
bus signals are generated. The direction of a transfer is de-
termined by the sequence (‘‘protocol’’) established by the
instruction under execution; but the CPU indicates the direc-
tion on the DDIN pin for hardware debugging purposes.
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (AD0–AD7), and a
Word operand is transferred on the entire bus. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-signif-
icant word to most-significant.
Figure 3-27 shows the NS32FX16 and FPU connection dia-
gram.
TL/EE/10818–34
Note:
CPU samples Data Bus here.
FIGURE 3-25. Slave Processor Read Cycle
TL/EE/10818–35
*
Note:
Slave Processor samples Data Bus here.
FIGURE 3-26. Slave Processor Write Cycle
3.5.5.8 Data Access Sequences
The 24-bit address provided by the NS32FX16 is a byte
address; that is, it uniquely identifies one of up to
16,777,216 8-bit memory locations. An important feature of
the NS32FX16 is that the presence of a 16-bit data bus
imposes no restrictions on data alignment; any data item,
regardless of size, may be placed starting at any memory
address. The NS32FX16 provides a special control signal,
High Byte Enable (HBE), which facilitates individual byte ad-
dressing on a 16-bit bus.
Memory is organized as two 8-bit banks, each bank receiv-
ing the word address (A1–A23) in parallel. One bank, con-
nected to Data Bus pins AD0–AD7, is enabled to respond
to even byte addresses; i.e., when the least significant ad-
dress bit (A0) is low. The other bank, connected to Data Bus
pins AD8–AD15, is enabled when HBE is low. See Figure
3-28.
Any bus cycle falls into one of three categories: Even Byte
Access, Odd Byte Access, and Even Word Access. All ac-
cesses to any data type are made up of sequences of these
cycles. Table 3-7 gives the state of A0 and HBE for each
category.
51
相關PDF資料 |
PDF描述 |
|---|---|
| NS32FX16-25 | Imaging/Signal Processor |
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復。