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| 型號： | NS32FX16-20 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號處理器 |
| 文件頁數(shù)： | 54/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-20 |
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3.0 Functional Description
(Continued)
3.5.5.9 Bus Access Control
The NS32FX16 CPU has the capability of relinquishing its
control of the bus upon request from a DMA controller or
another CPU. This capability is implemented by means of
the HOLD (Hold Request) and HLDA (Hold Acknowledge)
pins. By asserting HOLD low, an external device requests
access to the bus. On receipt of HLDA from the CPU, the
device may perform bus cycles, as the CPU at this point has
set AD0–AD15, A16–A23 and HBE to the TRI-STATE
é
condition and has switched ADS and DDIN to the input
mode. ALE is asserted in T4, and stays high during the time
the bus is granted. The CPU now monitors ADS and DDIN
from the external device to generate the relevant strobe
signals (i.e., TSO, DBE, RD or WR). To return control of the
bus to the CPU, the device sets HOLD inactive, and the
CPU acknowledges it by setting HLDA inactive.
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made,
as the CPU must always complete the current bus cycle.
Figure 3-29 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immedi-
ately following clock cycle.Figure 3-30 shows the sequence
when the CPU is using the bus at the time the HOLD re-
quest is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
Note 1:
During DMA cycles the WAIT1–2 signals should be kept inactive,
unless they are also monitored by the DMA controller. If wait states
are required, CWAIT should be used.
Note 2:
The logic value of the status pins, ST0–3, is undefined during DMA
activity.
54
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PDF描述 |
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| NS32FX16-25 | Imaging/Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
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| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
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