參數(shù)資料
型號(hào)： NS32FX16-20
廠商： National Semiconductor Corporation
英文描述： Imaging/Signal Processor
中文描述： 影像/信號(hào)處理器
文件頁(yè)數(shù)： 36/88頁(yè)
文件大小： 902K
代理商： NS32FX16-20
3.0 Functional Description
(Continued)
3.2.7 Exception Acknowledge Sequences:
Detailed Flow
For purposes of the following detailed discussion of excep-
tion acknowledge sequences, a single sequence called
‘‘service’’ is defined in Figure 3-11.
Upon detecting any interrupt request or trap condition, the
CPU first performs a sequence dependent upon the type of
exception. This sequence will include saving a copy of the
Processor Status Register and establishing a vector and a
return address. The CPU then performs the service se-
quence.
3.2.7.1 Maskable/Non-Maskable Interrupt Sequence
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, or Graphics instructions which have interior
loops (BBOR, BBXOR, BBAND, BBFOR, EXTBLT, MOVMP,
SBITPS, TBITS), at the next interruptible point during its ex-
ecution. The graphics instructions are interruptible.
1. If a String instruction was interrupted and not yet com-
pleted:
a. Clear the Processor Status Register P bit.
b. Set ‘‘Return Address’’ to the address of the first byte
of the interrupted instruction.
Otherwise, set ‘‘Return Address’’ to the address of the
next instruction.
2. Copy the Processor Status Register (PSR) into a tempo-
rary register, then clear PSR bits S, U, T, P and I.
3. If the interrupt is Non-Maskable:
a. Read a byte from address FFFF00
16
, applying Status
Code 0100 (Interrupt Acknowledge, Master: Section
3.4.1). Discard the byte read.
b. Set ‘‘Vector’’ to 1.
c. Go to Step 8.
4. If the interrupt is Non-Vectored:
a. Read a byte from address FFFE00
16
, applying Status
Code 0100 (Interrupt Acknowledge, Master: Section
3.4.1). Discard the byte read.
b. Set ‘‘Vector’’ to 0.
c. Go to Step 8.
5. Here the interrupt is Vectored. Read ‘‘Byte’’ from ad-
dress FFFE00
16
, applying Status Code 0100 (Interrupt
Acknowledge, Master: Section 3.4.1).
6. If ‘‘Byte’’
t
0, then set ‘‘Vector’’ to ‘‘Byte’’ and go to
Step 8.
7. If ‘‘Byte’’ is in the range
b
16 through
b
1, then the inter-
rupt source is Cascaded. (More negative values are re-
served for future use.) Perform the following:
a. Read the 32-bit Cascade Address from memory. The
address is calculated as INTBASE
a
4
*
Byte.
b. Read ‘‘Vector’’, applying the Cascade Address just
read and Status Code 0101 (Interrupt Acknowledge,
Cascaded: Section 3.4.1).
8. Perform Service (Vector, Return Address), Figure 3-11.
3.2.7.2 SLAVE/ILL/SVC/DVZ/FLG/BPT/UND
Trap Sequence
1. Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2. Set ‘‘Vector’’ to the value corresponding to the trap type.
SLAVE: Vector
e
3.
ILL:
Vector
e
4.
SVC:
Vector
e
5.
DVZ:
Vector
e
6.
FLG:
Vector
e
7.
BPT:
Vector
e
8.
UND:
Vector
e
10.
3. If Trap (UND)
a. Clear the Processor Status Register P Bit.
4. Copy the Processor Status Register (PSR) into a tempo-
rary register, then clear PSR bits T, U, S, and P.
5. Set ‘‘Return Address’’ to the address of the first byte of
the trapped instruction.
6. Perform Service (Vector, Return Address), Figure 3-11.
3.2.7.3. Trace Trap Sequence
1. In the Processor Status Register (PSR), clear the P bit.
2. Copy the PSR into a temporary register, then clear PSR
bits S, U and T.
3. Set ‘‘Vector’’ to 9.
4. Set ‘‘Return Address’’ to the address of the next instruc-
tion.
5. Perform Service (Vector, Return Address), Figure 3-11.
Service (Vector, Return Address):
1. Push the PSR copy onto the Interrupt Stack as a 16-
bit value.
2. Read the 32-bit External Procedure Descriptor from
the
Interrupt
Dispatch
tor
*
4
a
INTBASE Register contents.
3. Move the Module field of the Descriptor into the tem-
porary MOD Register.
Table:
address
is
Vec-
4. Read the Program Base pointer from memory ad-
dress MOD
a
8, and add to it the Offset field from
the Descriptor, placing the result in the Program
Counter.
5. Read the new Static Base pointer from the memory
address contained in MOD, placing it into the SB
Register.
6. Flush Queue: Non-sequentially fetch first instruction
of Interrupt Routine.
7. Push MOD Register onto the Interrupt Stack as a 16-
bit value. (The PSR has already been pushed as a 16-
bit value.)
8. Push the Return Address onto the Interrupt Stack as
a 32-bit quantity.
9. Copy temporary MOD Register to MOD Register.
FIGURE 3-11. Service Sequence
Invoked during All Interrupt/Trap Sequences
36
相關(guān)PDF資料
PDF描述
NS32FX16-25 Imaging/Signal Processor
NS32FX164-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FV16-25 Advanced Imaging/Communication Signal Processors
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX16-25 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor
NS32FX164 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX164-20 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164-25 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164AV-25 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
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