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| 型號： | NS32FX16-20 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號處理器 |
| 文件頁數(shù)： | 46/88頁 |
| 文件大小： | 902K |
| 代理商： | NS32FX16-20 |
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3.0 Functional Description
(Continued)
At this time the signals TSO (Timing State Output), DBE
(Data Buffer Enable) and either RD (Read Strobe) or WR
(Write Strobe) will also be activated.
The T3 state provides for access time requirements, and it
occurs at least once in a bus cycle. At the end of T2, on the
rising edge of CTTL, the CWAIT and WAIT1–2 signals are
sampled to determine whether the bus cycle will be extend-
ed. See Section 3.5.5.3.
If the CPU is performing a read cycle, the data bus (AD0–
AD15) is sampled at the beginning of T4 on the rising edge
of CTTL. Data must, however, be held a little longer to meet
the data hold time requirements. The RD signal is guaran-
teed not to go inactive before this time, so its rising edge
can be safely used to disable the device providing the input
data.
The T4 state finishes the bus cycle. At the beginning of T4,
the RD or WR, and TSO signals go inactive, and on the
falling edge of CTTL, DBE goes inactive, having provided for
necessary data hold times. Data during Write cycles re-
mains valid from the CPU throughout T4. Note that the Bus
Status lines (ST0–ST3) change at the beginning of T4, an-
ticipating the following bus cycle (if any).
3.5.5.3 Cycle Extension
To allow sufficient access time for any speed of memory or
peripheral device, the NS32FX16 provides for extension of
a bus cycle. Any type of bus cycle except a Slave Processor
cycle and a special bus cycle can be extended.
InFigures 3-21 and3-22, note that during T3 all bus control
signals from the CPU are flat. Therefore, a bus cycle can be
cleanly extended by causing the T3 state to be repeated.
This is the purpose of the WAIT1–2 and CWAIT input sig-
nals.
At the end of state T2, on the rising edge of CTTL, WAIT1–
2 and CWAIT are sampled.
If any of these signals are active, the bus cycle will be ex-
tended by at least one clock cycle. Thus, one or more addi-
tional T3 state (also called wait state) will be inserted after
the next T-State. Any combination of the above signals can
be activated at one time. However, the WAIT1–2 inputs are
only sampled by the CPU at the end of state T2. They are
ignored at all other times.
The WAIT1–2 inputs are binary weighted, and can be used
to insert up to 3 wait states, according to the following table.
WAIT2
WAIT1
Number of
Wait States
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
0
1
2
3
CWAIT causes wait states to be inserted continuously as
long as it is sampled active. It is normally used when the
number of wait states to be inserted in the CPU bus cycle is
not known in advance.
The following sequence shows the CPU response to the
WAIT1–2 and CWAIT inputs.
1. Start bus cycle.
2. Sample WAIT1–2 and CWAIT at the end of state T2.
3. If the WAIT1–2 inputs are both inactive, then go to step
6.
4. Insert
WAIT1–2.
the
number
of
wait
states
selected
by
5. Sample CWAIT again.
6. If CWAIT is not active, then go to step 8.
7. Insert one wait state and then go to step 5.
8. Complete bus cycle.
Figure 3-23 shows a bus cycle extended by three wait
states, two of which are due to WAIT2, and one is due to
CWAIT.
46
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32FX16-25 | Imaging/Signal Processor |
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
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