
Table of Contents
(Continued)
4.0 DEVICE SPECIFICATIONS
4.1 NS32FX16 Pin Descriptions
4.1.1 Supplies
4.1.2 Input Signals
4.1.3 Output Signals
4.1.4 Input-Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
4.4.2.2 Input Signal Requirements
4.4.3 Timing Diagrams
Appendix A: INSTRUCTION FORMATS
Appendix B: INSTRUCTION EXECUTION TIMES
B.1 Basic and Floating-Point Instructions
B.1.1 Equations
B.1.2 Notes on Table Use
B.1.3 Calculation of the Execution Time TEX for Basic
Instructions
B.1.4 Calculation of the Execution Time TEX for
Floating-Point Instructions
B.2 Special Graphics Instructions
B.2.1 Execution Time Calculation for Special
Graphics Instructions
B.3 DSPM Instructions
List of Illustrations
CPU Block Diagram àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà1-1
NS32FX16 Internal Registersàààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-1
Processor Status Register (PSR)ààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-2
Configuration Register (CFG) àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-3
DSP Module Registers Address Map ààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-4
CPTR Register Formatàààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-5
CTL Register Format ààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-6
ST Register Format àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-7
On-Chip RAM Array Address Map àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-8
NS32FX16 Address Mapping àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-9
NS32FX16 Run-Time Environment àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-10
General Instruction Formatààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-11
Index Byte Format àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-12
Displacement Encodingsààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-13
Correspondence between Linear and Cartesian Addressing àààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-14
32-Pixel by 32-Scan Line Frame Bufferààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-15
Overlapping BITBLT Blocks àààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààààà2-16
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