參數(shù)資料
型號(hào)： NS32FX16-20
廠商： National Semiconductor Corporation
英文描述： Imaging/Signal Processor
中文描述： 影像/信號(hào)處理器
文件頁(yè)數(shù)： 39/88頁(yè)
文件大?。?/td> 902K
代理商： NS32FX16-20
3.0 Functional Description
(Continued)
3.4.2 Complex Number Representation
The complex numbers processed by the DSP Module are
given by pairs of 16-bit Fixed-Point values representing the
real and imaginary parts of the number. The range of these
values is defined by the interval
[
x:
b
1
s
x
k
1
]
.
The values are represented in 2’s complement notation and
the decimal point is between bits 14 and 15.
The intermediate results of vector operations are stored in
temporary 32-bit registers in order to maintain full accuracy.
Whenever data is transferred from the accumulator, the
DSP module returns both the real and imaginary parts in
16-bit representation by rounding (to nearest) the least sig-
nificant bits of the temporary registers.
An overflow is detected whenever a temporary result is out-
side the range given above. When an overflow is detected,
the ST register OVF bit and either OP0 or OP1 is set to 1.
Complex numbers are stored in memory as two consecutive
16-bit words, with the word at the lower address represent-
ing the real part and the word at the higher address repre-
senting the imaginary part of the number.
Complex vectors consists of arrays of complex numbers
stored in consecutive memory locations. Complex vectors
must be aligned to double-word boundaries. Figure 3–13
shows the memory organization of a complex vector.
Memory
Addresses
Memory
Contents
D
Re( D
[
0
]
)
D
a
2
Im( D
[
0
]
)
D
a
4
Re( D
[
1
]
)
D
a
6
Im ( D
[
1
]
)
#
#
Re( D
[
n
]
)
D
a
4
*
n
D
a
4
*
n
a
2
Im( D
[
n
]
)
w
16-bit
x
FIGURE 3-13. Memory Organization
of a Complex Vector
3.4.3 DSPM Instructions
The DSP Module can execute the following vector instruc-
tions, in addition to the basic CPU load and store operations
on its internal registers.
VCMAD
Vector Complex Multiply Add
VCMUL
Vector Complex Multiply
VCMAC
Vector Complex Multiply Accumulate
VCMAG
Vector Complex Magnitude
The following terms are used in the description of the opera-
tions:
C
[
i
]
Coefficient memory element. Entry
[
i
]
can be select-
ed by the address generator or directly accessed by
the CPU.
D
[
i
]
Data from external memory fetched using the ad-
dress generator.
Y
D
[
i
]
#
Complex Multiplier input register.
The conjugate of D
[
i
]
.
A
Complex Accumulator.
Each DSP Module instruction is controlled by the CTL regis-
ter OPC and OPM fields. OPC is the basic opcode, while
OPM is an opcode modifier whose function is to further
qualify the operation specified by OPC.
Table 3-3 provides a summary of the various vector instruc-
tions executed by the DSP module.
A DSPM instruction starts whenever the software writes into
the CTL register.
Note that all the operands are complex numbers.
Thus,
A
e
R
(C
[
i
]
c
D
[
i
]
) breaks down to:
Re(A)
e
R
(Re(C
[
i
]
)
c
Re(D
[
I
]
)
b
Im(C
[
i
]
)
c
Im(D
[
i
]
)
ó
Im(A)
e
R
(Re(C
[
i
]
)
c
Im(D
[
i
]
)
a
Im(C
[
i
]
)
c
Re(D
[
i
]
)
ó
Note:
The accumulator A, the multipiler input register Y, the external data
pointer DPTR and the coefficient pointer CPTR registers are used as
temporary registers during vector instructions. The values previously
stored in these registers are destroyed.
TABLE 3-3. DSPM Instructions Summary
Instruction
OPC
OPM
Operation
00
00
00
00
0
0
1
1
0
1
0
1
C
[
i
]
k
e
C
[
i
]
a
Y x D
[
i
]
C
[
i
]
k
e
C
[
i
]
a
Y x D
[
i
]
#
C
[
i
]
k
e
Y x D
[
i
]
C
[
i
]
k
e
Y x D
[
i
]
#
VCMAD
01
01
01
01
0
0
1
1
0
1
0
1
C
[
i
]
k
e
C
[
i
]
x (1
a
D
[
i
]
)
C
[
i
]
k
e
C
[
i
]
x (1
a
D
[
i
]
#
)
C
[
i
]
k
e
C
[
i
]
x D
[
i
]
C
[
i
]
k
e
C
[
i
]
x D
[
i
]
#
VCMUL
10
10
10
10
0
0
1
1
0
1
0
1
A
k
e
A
a
R
(C
[
i
]
x D
[
i
]
)
A
k
e
A
a
R
(C
[
i
]
x D
[
i
]
#
)
A
k
e
R
(C
[
i
]
x D
[
i
]
)
A
k
e
R
(C
[
i
]
x D
[
i
]
#
)
VCMAC
11
11
11
11
0
0
1
1
0
1
0
1
A
k
e
A
a
R
(C
[
i
]
x C
[
i
]
)
A
k
e
A
a
R
(C
[
i
]
x C
[
i
]
#
)
A
k
e
R
(C
[
i
]
x C
[
i
]
)
A
k
e
R
(C
[
i
]
x C
[
i
]
#
)
VCMAG
3.4.4 Circular Buffers
The DSP Module accesses arrays of data in external memo-
ry using the DPTR register as an address pointer. The DS
field in the CTL register controls the size of the array. The
DSPM handles the data in the external array in a circular
fashion. Only the appropriate number of least significant ad-
dress bits in the DPTR register are incremented after each
memory access. The upper bits remain unchanged. Table 3-
4 shows which bits are incremented for various buffer sizes.
39
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