參數(shù)資料
型號(hào)： MT47H64M16HR-3IT
元件分類： DRAM
英文描述： 64M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84
文件頁數(shù)： 83/129頁
文件大?。?/td> 9252K
代理商： MT47H64M16HR-3IT
Table 30: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe
All units are shown in picoseconds
DQ
Slew
Rate
(V/ns)
DQS, DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
2.0
125
45
125
45
125
45
–
1.5
83
21
83
21
83
21
95
33
–
1.0
0
12
24
–
0.9
–
–11
–14
–11
–14
1
–2
13
10
25
22
–
0.8
–
–25
–31
–13
–19
–1
–7
11
5
23
17
–
0.7
–
–31
–42
–19
–30
–7
–18
5
–6
17
6
–
0.6
–
–43
–59
–31
–47
–19
–35
–7
–23
5
–11
0.5
–
–74
–89
–62
–77
–50
–65
–38
–53
0.4
–
–127 –140 –115 –128 –103 –116
Notes: 1. For all input signals, the total tDS and tDH required is calculated by adding the data
sheet value to the derating value listed in Table 30.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-
ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line
between the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 27 (page 61)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “VREF(DC) to AC region,” the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for the derating value (see
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC)min and the first cross-
ing of VREF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-
rating value (see Figure 29 (page 62)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to VREF(DC) region,” the slew rate of a tan-
gent line to the actual signal from the DC level to VREF(DC) level is used for the derating
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 32 (page 59) are the
DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to VREF is listed in Table 34 (page 60) and
Table 35 (page 60). Table 34 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-533. Table 35 provides the VREF-based fully derated values for
the DQ (tDSa and tDHa) for DDR2-400.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Input Slew Rate Derating
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
57
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H64M16HR-3L 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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