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參數(shù)資料
| 型號(hào)： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 122/129頁 |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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Figure 48: READ Interrupted by READ
T0
T1
T2
Don’t Care
Transitioning Data
T3
T4
T5
T6
Command
READ1
NOP2
Valid
READ3
Valid
T7
T8
T9
CK
CK#
CL = 3 (AL = 0)
tCCD
Address
Valid4
CL = 3 (AL = 0)
DQ
DO
A10
Valid5
DQS, DQS#
Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is-
sued to banks used for READs at T0 and T2.
3. Interrupting READ command must be issued exactly 2 × tCK from previous READ.
4. READ command can be issued to any valid bank and row address (READ command at T0
and T2 can be either same bank or different bank).
5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-
terrupting READ command.
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 49: READ-to-WRITE
CK
CK#
T0
T1
T2
Don’t Care
Transitioning Data
T3
T4
T5
T6
T7
T8
T9
T10
T11
AL = 2
CL = 3
RL = 5
WL = RL - 1 = 4
tRCD = 3
Command
ACT n
NOP
READ n
NOP
WRITE
DQS, DQS#
DQ
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
DI
n
DI
n + 1
DI
n + 2
DI
n + 3
Notes: 1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
READ with Precharge
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and
tRTP. tRTP is the minimum time from the rising clock edge that initiates the last 4-bit
prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time
from the actual READ (AL after the READ command) to PRECHARGE command. For
BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command.
Following the PRECHARGE command, a subsequent command to the same bank can-
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
READ
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
92
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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