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參數(shù)資料
| 型號： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 75/129頁 |
| 文件大小： | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16
Table 4: Input Capacitance ............................................................................................................................ 21
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 22
Table 6: Temperature Limits .......................................................................................................................... 23
Table 7: Thermal Impedance ......................................................................................................................... 23
Table 8: General IDD Parameters .................................................................................................................... 24
Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 25
Table 10: DDR2 IDD Specifications and Conditions (Die Revision G) ................................................................ 26
Table 11: AC Operating Specifications and Conditions .................................................................................... 29
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 38
Table 13: ODT DC Electrical Characteristics ................................................................................................... 39
Table 14: Input DC Logic Levels ..................................................................................................................... 40
Table 15: Input AC Logic Levels ..................................................................................................................... 40
Table 16: Differential Input Logic Levels ........................................................................................................ 41
Table 17: Differential AC Output Parameters .................................................................................................. 43
Table 18: Output DC Current Drive ................................................................................................................ 43
Table 19: Output Characteristics .................................................................................................................... 44
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 45
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 46
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 47
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 48
Table 24: Input Clamp Characteristics ........................................................................................................... 49
Table 25: Address and Control Balls ............................................................................................................... 50
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 50
Table 27: AC Input Test Conditions ................................................................................................................ 51
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) ................................................... 53
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) .......................................... 54
Table 30: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ..................................................... 57
Table 31: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................ 58
Table 32: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb .................................................. 59
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ..................................... 59
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ..................................... 60
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ..................................... 60
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 65
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 66
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 68
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 69
Table 40: Burst Definition .............................................................................................................................. 73
Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 94
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 100
Table 43: Truth Table – CKE ......................................................................................................................... 115
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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