- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296642 > MT47H64M16HR-3IT 64M X 16 DDR DRAM, 0.4 ns, PBGA84 PDF資料下載
參數(shù)資料
| 型號： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 62/129頁 |
| 文件大小： | 9252K |
| 代理商： | MT47H64M16HR-3IT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當(dāng)前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5
+ 0.03, or 2.53, for tAOF (MAX).
46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance be-
gins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully on.
Both are measured from tAOND.
47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT
turn off time tAOF (MAX) is when the bus is in High-Z. Both are measured from tAOFD.
48. Half-clock output parameters must be derated by the actual tERR5per and tJITdty when
input clock jitter is present; this will result in each parameter becoming larger. The pa-
rameter tAOF (MIN) is required to be derated by subtracting both tERR5per (MAX) and
tJITdty (MAX). The parameter tAOF (MAX) is required to be derated by subtracting both
tERR5perx (MIN) and tJITdty (MIN).
49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1,000 but it will likely be
3 x tCK + tAC (MAX) + 1,000 in the future.
50. Should use 8 tCK for backward compatibility.
AC and DC Operating Conditions
Table 12: Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS
Parameter
Symbol
Min
Nom
Max
Units
Notes
Supply voltage
VDD
1.5
1.55
1.9
V
VDDL supply voltage
VDDL
1.5
1.55
1.9
V
I/O supply voltage
VDDQ
1.5
1.55
1.9
V
I/O reference voltage
VREF(DC)
0.49 × VDDQ
0.50 × VDDQ
0.51 × VDDQ
V
I/O termination voltage (system)
VTT
VREF(DC) - 40
VREF(DC)
VREF(DC) + 40
mV
Notes: 1. VDD and VDDQ must track each other. If VDD < 1.7V, then VDD - 0.05V ≤ VDDQ ≤ VDD; else
VDD - 0.1V ≤ VDDQ ≤ VDD.
2. VSSQ = VSSL = VSS.
3. VDDQ tracks with VDD; VDDL tracks with VDD.
4. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed
±1% of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2% of VREF(DC).
This measurement is to be taken at the nearest VREF bypass capacitor.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, is expected to be set equal to VREF, and must track variations in the DC level of
VREF.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
AC and DC Operating Conditions
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC4M32LFB5-10ES:G | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| MT48V4M32TG-8XT | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。