參數(shù)資料
型號(hào)： MT47H64M16HR-3IT
元件分類： DRAM
英文描述： 64M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84
文件頁數(shù)： 55/129頁
文件大?。?/td> 9252K
代理商： MT47H64M16HR-3IT
Table 11: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = +1.5–1.9V, VDD = +1.5–1.9V
AC Characteristics
-25E
-25
-3E
-3
-37E
Units
Notes
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Data-Out
DQ output access time
from CK/CK#
tAC
–400
+400
–400
+400
–450
+450
–450
+450
–500
+500
ps
DQS–DQ skew, DQS to
last DQ valid,
per group,
per access
tDQSQ
–
200
–
200
–
240
–
240
–
300
ps
DQ hold from next DQS
strobe
tQHS
–
300
–
300
–
340
–
340
–
400
ps
DQ–DQS hold, DQS to
first DQ not valid
tQH
MIN = tHP - tQHS
MAX = n/a
ps
CK/CK# to DQ, DQS
High-Z
tHZ
MIN = n/a
MAX = tAC (MAX)
ps
CK/CK# to DQ Low-Z
tLZ2
MIN = 2 × tAC (MIN)
MAX = tAC (MAX)
ps
Data valid output
window
DVW
MIN = tQH - tDQSQ
MAX = n/a
ns
Data-In
DQ and DM input setup
time to DQS
tDSb
50
–
50
–
100
–
100
–
100
–
ps
DQ and DM input hold
time to DQS
tDHb
125
–
125
–
175
–
175
–
225
–
ps
DQ and DM input setup
time to DQS
tDSa
250
–
250
–
300
–
300
–
350
–
ps
DQ and DM input hold
time to DQS
tDHa
250
–
250
–
300
–
300
–
350
–
ps
DQ and DM input pulse
width
tDIPW
MIN = 0.35 × tCK
MAX = n/a
tCK
1Gb:
x4,
x8,
x16
1.55V
DDR2
SDRAM
AC
Timing
Operating
Specifications
PDF:
09005aef82b91d01
1GbDDR2_1_55V.PDF
Rev.
A
5/09
EN
31
Micron
Technology,
Inc.
reserves
the
right
to
change
products
or
specifications
without
notice.
2009
Micron
Technology,
Inc.
All
rights
reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H64M16HR-3L 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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