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Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. H 7/05 EN
60
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 41:
Bank Write with Auto Precharge
Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. Burst length = 4, AL = 0, and WL = 2 shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = row address, BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
7. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
8. WR is programmed via MR[11, 10, 9] and is calculated by dividing tWR (in ns) by tCK and
rounding up to the next integer value.
9. Subsequent rising DQS signals must align to the clock within tDQSS.
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
RA
tRCD
tRAS
tRP
WR8
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T6n
NOP5
COMMAND4
3
ACT
RA
Col n
WRITE2
NOP5
Bank x
NOP5
Bank x
NOP5
tDQSL tDQSH tWPST
DQ1
DM
WL ± tDQSS (NOM)
DON’T CARE
TRANSITIONING DATA
tWPRE
DQS,DQS#
ADDRESS
T9
NOP5
WL = 2
DI
n
9