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參數(shù)資料
| 型號： | MT47H32M16BT-37VL:A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| 封裝： | 11 X 19 MM, LEAD FREE, FBGA-92 |
| 文件頁數(shù)： | 105/126頁 |
| 文件大?。?/td> | 7045K |
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pdf: 09005aef8117c18e, source: 09005aef8117c192
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. H 7/05 EN
8
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
General Description
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read, or a burst write of eight with another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs
allows for concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
Notes:
1. The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
2. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7), DM refers to LDM and DQS refers to LDQS.
For the upper byte (DQ8 through DQ15), DM refers to UDM and DQS refers to UDQS.
3. Complete functionality is described throughout the document and any page or dia-
gram may have been simplified to convey a topic and may not be inclusive of all
requirements.
4. Any specific requirement takes precedence over a general statement.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H32M16CC-37E | 制造商:Micron Technology Inc 功能描述: |
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