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Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_3.fm - Rev. H 7/05 EN
110
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
IDD Specifications and Conditions
Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C
≤ T
C ≤ +85°C.
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
-37V VDDQ = +1.9V ±0.1V, VDDL = +1.9V ±0.1.
2. Input slew rate is specified by AC Parametric Test Conditions.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD Conditions:
LOW is defined as VIN
≤ VIL(AC) MAX.
HIGH is defined as VIN
≥ VIH(AC) MIN.
Stable is defined as inputs stable at a HIGH or LOW level.
Floating is defined as inputs at VREF = VDDQ/2.
Switching is defined as inputs changing between HIGH and LOW every other clock cycle
(once per two clocks) for address and control signals.
Switching is defined as inputs changing between HIGH and LOW every other data transfer
(once per clock) for DQ signals, not including masks or strobes.
6. IDD1, IDD4R, and Idd7 require A12 in EMR1 to be enabled during testing.
Operating bank interleave read current: All bank
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL =
tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD
= tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH
between valid commands; address bus inputs are stable
during deselects; data bus inputs are switching; see “IDD7
Conditions” for detail.
IDD7
x4, x8
280
270
300
260
230
mA
x16
340
330
370
325
320
Table 43:
DDR2 IDD Specifications and Conditions (Continued)
Notes: 1–6; notes appear on page 110
Parameter/Condition
Sym
Config
-3E
-3
-37V -37E
-5E
Units