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| 型號(hào)： | MT47H32M16BT-37VL:A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| 封裝： | 11 X 19 MM, LEAD FREE, FBGA-92 |
| 文件頁(yè)數(shù)： | 43/126頁(yè) |
| 文件大?。?/td> | 7045K |
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pdf: 09005aef8117c18e, source: 09005aef8117c192
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. H 7/05 EN
23
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CL, operating mode,
DLL reset, write recovery, and power-down mode, as shown in Figure 10. Contents of the
mode register can be altered by re-executing the LOAD MODE (LM) command. If the
user chooses to modify only a subset of the MR variables, all variables (M0–M14) must
be programmed when the LOAD MODE command is issued.
The mode register is programmed via the LM command (bits BA1–BA0 = 0, 0) and other
bits (M13–M0 for x4 and x8, M12–M0 for x16) will retain the stored information until it is
programmed again or the device loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory array, pro-
vided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state. The controller must wait the specified time tMRD before initiating any subsequent
operations such as an ACTIVE command. Violating either of these requirements will
result in unspecified operation.
Burst Length
Burst length is defined by bits M0–M3, as shown in Figure 10. Read and write accesses to
the DDR2 SDRAM are burst-oriented, with the burst length being programmable to
either four or eight. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most
significant column address bit for a given configuration). The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting location within the block. The pro-
grammed burst length applies to both READ and WRITE bursts.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H32M16CC-37E | 制造商:Micron Technology Inc 功能描述: |
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