- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄299522 > MT47H32M16BT-37VL:A 32M X 16 DDR DRAM, 0.5 ns, PBGA92 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT47H32M16BT-37VL:A |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| 封裝： | 11 X 19 MM, LEAD FREE, FBGA-92 |
| 文件頁(yè)數(shù)： | 28/126頁(yè) |
| 文件大?。?/td> | 7045K |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)
pdf: 09005aef8117c18e, source: 09005aef8117c192
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_3.fm - Rev. H 7/05 EN
123
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Notes
25. Operating frequency is only allowed to change during self refresh mode (See “Self
Refresh” on page 28), precharge power-down mode (See “Power-Down Mode” on
page 31), and system reset condition (see “Reset Function (CKE Low Anytime)” on
page 2.
26. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance
begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully
on. Both are measured from tAOND.
27. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance.
ODT turn off time tAOF (MAX) is when the bus is in High-Z. Both are measured from
tAOFD.
28. This parameter has a two clock minimum requirement at any tCK.
29. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed
prior to CK, CK# being removed in a system RESET condition. “Reset Function (CKE
Low Anytime)” on page 2.
30. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in
Figure 68 on page 30.
31. No more than four bank-ACTIVE commands may be issued in a given tFAW (MIN)
period. tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all
8-bank DDR2 devices, regardless of the number of banks already open or closed.
32. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
the number of banks already open or closed. If a single-bank PRECHARGE command
is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
33. Value is minimum pulse width, not the number of clock registrations.
34. This is applicable to READ cycles only. WRITE cycles generally require additional time
due to tWR during auto precharge.
35. tCKE (MIN) of three clocks means CKE must be registered on three consecutive posi-
tive clock edges. CKE must remain at the valid input level the entire time it takes to
achieve the three clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
36. This parameter is not referenced to a specific voltage level, but specified when the
device output is no longer driving (tRPST) or beginning to drive (tRPRE).
37. When DQS is used single-ended, the minimum limit is reduced by 100ps.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H64M16HQ-3IT:G | 64M X 16 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M8CF-5EAT:F | DDR DRAM, PBGA60 |
| MT48H16M16LFBF-10IT | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16A2BB-6ALIT:G | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| MT49H8M36HU-33 | 8M X 36 DDR DRAM, 0.3 ns, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H32M16CC-37E | 制造商:Micron Technology Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。