參數(shù)資料
型號： MT47H32M16BT-37VL:A
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.5 ns, PBGA92
封裝： 11 X 19 MM, LEAD FREE, FBGA-92
文件頁數(shù)： 68/126頁
文件大小： 7045K
pdf: 09005aef8117c18e, source: 09005aef8117c192
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. H 7/05 EN
46
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
tRP)* (see Figure 25 on page 46); where * means each parameter term is divided by tCK
and rounded up to the next integer. In any event, internal precharge does not start ear-
lier than two clocks after the last 4-bit prefetch.
Figure 24:
READ to PRECHARGE BL = 4
Figure 25:
READ to PRECHARGE BL = 8
Figure 26:
READ to WRITE
DOUT
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3
READ
Read Latency = 4 (AL = 1, CL = 3), BL = 4, tRTP
≥ 2 clocks
Shown with nominal tAC, tDQSCK, and tDQSQ
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
NOP
PRECHARGE
DOUT
T3
T4
T5
T6
ACTIVE
T7
ADDRESS
A10
AL = 1
NOP
Bank a
≥tRTP (MIN)
Bank a
≥tRAS (MIN)
Bank a
≥tRP (MIN)
NOP
AL + BL/2 + tRTP - 2 clocks
NOP
≥tRC (MIN)
4-bit
prefetch
Valid
DOUT
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3
READ
RL = 4 (AL = 1, CL = 3), BL = 8, tRTP
≥ 2 clocks
Shown with nominal tAC, tDQSCK, and tDQSQ
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
NOP
DOUT
T3
T4
T5
T6
T7
T8
ADDRESS
A10
AL = 1
NOP
Bank a
≥tRC (MIN)
≥tRTP (MIN)
NOP
DOUT
first 4-bit
prefetch
second 4-bit
prefetch
≥tRP (MIN)
PRECHARGE
Bank a
NOP
AL + BL/2 + tRTP - 2 clocks
NOP
ACTIVE
≥tRAS (MIN)
Valid
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
AL = 2
ACTIVE n
BL = 4
Shown with nominal tAC, tDQSCK, and tDQSQ
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
NOP
DOUT
n
T3
T4
T5
NOP
WRITE n
T6
NOP
Din
n + 3
Din
n + 2
Din
n + 1
WL = RL - 1 = 4
T7
T8
NOP
Din
n
T9
T10
T11
NOP
CL = 3
RL = 5
CL = 3
AL = 2
tRCD = 3
READ n
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H32M16CC-37E 制造商:Micron Technology Inc 功能描述:
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