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| 型號(hào)： | MT47H32M16BT-37VL:A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| 封裝： | 11 X 19 MM, LEAD FREE, FBGA-92 |
| 文件頁(yè)數(shù)： | 112/126頁(yè) |
| 文件大小： | 7045K |
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pdf: 09005aef8117c18e, source: 09005aef8117c192
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_3.fm - Rev. H 7/05 EN
86
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage | VTR - VCP | required for switching, where
VTR is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary
input (such as CK#, DQS#, LDQS#, UDQS#). The minimum value is equal to VIH(DC) - VIL(DC).
Differential input signal levels are shown in Figure 67.
3. VID(AC) specifies the input differential voltage | VTR - VCP | required for switching, where
VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the complemen-
tary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The minimum value is equal to
VIH(AC) - VIL(AC), as shown in Table 21 on page 85.
4. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
differential input signals must cross, as shown in Figure 67.
5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is
expected to be approximately 0.5 x VDDQ.
Figure 67:
Differential Input Signal Levels
Notes: 1. This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2.
2. TR and CP must cross in this region.
3. TR and CP must meet at least VID(DC) MIN when static and is centered around VMP(DC).
4. TR and CP must have a minimum 500mV peak-to-peak swing.
5. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
8. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#, LDQS#, and UDQS# signals.
Table 22:
Differential Input Logic Levels
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Notes
DC Input Signal Voltage
VIN(DC)
-300
VDDQ + 300
mV
1
DC Differential Input Voltage
VID(DC)
250
VDDQ + 600
mV
2
AC Differential Input Voltage
VID(AC)
500
VDDQ + 600
mV
3
AC Differential Cross-Point Voltage
VIX(AC)
0.50 x VDDQ - 175
0.50 x VDDQ + 175
mV
4
Input Midpoint Voltage
VMP(DC)
850
950
mV
5
CP8
TR8
2.1V
@ VDDQ = 1.8V
2
3
VIN(DC) MAX5
VIN(DC) MIN
5
4
- 0.30V
0.9V
1.075V
0.725 V
VID(AC)
VID(DC)
X
VMP(DC)1
VIX(AC)
X
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT47H32M16CC-37E | 制造商:Micron Technology Inc 功能描述: |
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