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參數(shù)資料
| 型號(hào)： | MT47H32M16BT-37VL:A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| 封裝： | 11 X 19 MM, LEAD FREE, FBGA-92 |
| 文件頁數(shù)： | 41/126頁 |
| 文件大?。?/td> | 7045K |
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pdf: 09005aef8117c18e, source: 09005aef8117c192
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. H 7/05 EN
21
2004, 2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. The following
sequence is required for power-up and initialization and is shown in Figure 9.
1. Apply power; if CKE is maintained below 0.2 x VDDQ, outputs remain disabled. To guar-
antee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied
to the ODT pin (all other inputs may be undefined). The time from when VDD first
starts to power-up to the completion of VDDQ must be equal to or less than 20ms; sig-
nals must not have any slope reversals during ramp up. At least one of the following
two sets of conditions (A or B) must be met:
A.CONDITION SET A
VDD, VDDL, and VDDQ are driven from a single power converter output
VTT is limited to 0.95V MAX
VREF tracks VDDQ/2
B. CONDITION SET B
Apply VDD before or at the same time as VDDL
Apply VDDL before or at the same time as VDDQ
Apply VDDQ before or at the same time as VTT and VREF
The voltage difference between any VDD supply cannot exceed 0.3V
3. For a minimum of 200s after stable power and clock (CK, CK#), apply NOP or DESE-
LECT commands and take CKE high
4. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
5. Issue an LOAD MODE command to the EMR(2) register. (To issue an EMR(2) com-
mand, provide LOW to BA0, provide HIGH to BA1.)
6. Issue a LOAD MODE command to the EMR(3) register. (To issue an EMR(3) com-
mand, provide HIGH to BA0 and BA1.)
7. Issue an LOAD MODE command to the EMR register to enable DLL. To issue a DLL
Enable command, provide LOW to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and
E9 must all be set to 0.
8. Issue a LOAD MODE command for DLL Reset. 200 cycles of clock input is required to
lock the DLL. (To issue a DLL reset, provide HIGH to A8 and provide LOW to BA1, and
BA0.) CKE must be HIGH the entire time.
9. Issue PRECHARGE ALL command.
10. Issue two or more REFRESH commands.
11. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to
program operating parameters without resetting the DLL).
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7,
E8, and E9 to 1 and set all other desired parameters.
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8,
and E9 to 0 and set all other desired parameters.
The DDR2 SDRAM is now initialized and ready for normal operation 200 clocks after
DLL reset (in step 8).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H32M16CC-37E | 制造商:Micron Technology Inc 功能描述: |
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