參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 88/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
89
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams
Figure 50:
Bank Read - With Auto Precharge
Notes: 1. DOn = data-out from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. The READ command can only be applied at T3 if tRAP is satisfied at T3.
7. tRP starts only after tRAS has been satisfied.
detailed DQS and DQ timing.
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS
tIH
tIS
tIH
IS
IH
RA
tRC
tRP7
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ1
DQS
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ1
DQS
tRPRE
tRPST
tDQSCK (MIN)
tDQSCK (MAX)
tAC (MIN)
tLZ (MIN)
DO
n
tHZ (MAX)
tAC (MAX)
DO
n
NOP5
COMMAND4
3
ACT
RA
Col n
READ2,6
NOP5
Bank x
RA
Bank x
ACT
Bank x
NOP5
DON’T CARE
TRANSITIONING DATA
tRAS
tLZ(MIN)
tRCD, tRAP6
x8: A12
x16: A11, A12
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
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