參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 37/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
42
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 26:
WRITE-to-READ – Interrupting
Notes: 1. DI b = data-in for column b, DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the
READ command would not mask these two data elements.
tDQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
ADDRESS
Bank a,
Col b
Bank a,
Col n
READ
T0
T1
T2
T3
T2n
T4
T5
T5n
T1n
T6
T6n
tWTR
CL = 2
DQ
DQS
DM
DI
b
DO
n
tDQSS (MIN)
CL = 2
DQ
DQS
DM
DI
b
tDQSS (MAX)
CL = 2
DQ
DQS
DM
DI
b
DO
n
DO
n
DON’T CARE
TRANSITIONING DATA
tDQSS
T3n
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