參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 78/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
8
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
General Description
Figure 2:
128 Meg x 4 Functional Block Diagram
Figure 3:
64 Meg x 8 Functional Block Diagram
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
12
COMMAND
DECODE
A0-A12,
BA0, BA1
CKE
13
ADDRESS
REGISTER
15
2048
(x8)
16384
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
15
BANK1
BANK2
BANK3
13
11
1
2
REFRESH
COUNTER
4
1
INPUT
REGISTERS
1
RCVRS
1
8
2
8
clk
out
DATA
DQS
MASK
DATA
CK
COL0
clk
in
DRVRS
DLL
MUX
DQS
GENERATOR
4
8
DQ0–
DQ3
DQS
DM
1
READ
LATCH
WRITE
FIFO
&
DRIVERS
COL0
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
11
COMMAND
DECODE
A0-A12,
BA0, BA1
CKE
13
ADDRESS
REGISTER
15
1024
(x16)
16384
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
15
BANK1
BANK2
BANK3
13
10
2
REFRESH
COUNTER
8
1
INPUT
REGISTERS
1
RCVRS
1
16
2
16
clk
out
DATA
DQS
MASK
DATA
CK
clk
in
DRVRS
DLL
MUX
DQS
GENERATOR
8
16
DQ0–
DQ7
DQS
1
READ
LATCH
WRITE
FIFO
&
DRIVERS
1
COL0
DM
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