參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 10/94頁(yè)
文件大小： 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
18
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Register Definition
CAS (READ) Latency
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2, 2.5, or
3 (DDR400 only) clocks, as shown in Figure 8.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 5 on page 19 indi-
cates the operating frequencies at which each CAS latency (CL) setting can be used.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
Figure 8:
CAS Latency (CL)
Note:
Burst Length = 4 in the cases shown; shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
READ
NOP
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON’T CARE
TRANSITIONING DATA
READ
NOP
CK
CK#
COMMAND
DQ
DQS
CL = 3
T0
T1
T2
T3
T3n
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