參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 77/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
79
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Notes
Figure 40:
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
Notes: 1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at
T2n are an “early DQS,” at T3 is a “nominal DQS,” and at T3n is a “l(fā)ate DQS.”
2. For a x4, only two DQ apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus
tDQSQ.
DQ (Last data valid)
DQ2
DQS1
DQ (Last data valid)
DQ (First data no longer valid)
All DQ and DQS, collectively6
Earliest signal transition
Latest signal transition
T2
T2n
T3
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH4
tHP5
tQH4
tHP5
tQH4
tDQSQ3
Data
Valid
Window
Data
Valid
Window
Data
Valid
Window
Data
Valid
Window
相關(guān)PDF資料
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