參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 39/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
44
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 28:
WRITE-to-PRECHARGE – Uninterrupting
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI
b.
3. An uninterrupted burst of 4 is shown.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
and WRITE commands may be to different devices, in which case tWR is not required and
the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
tDQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
PRE7
NOP
ADDRESS
Bank a,
Col b
Bank,
(a or all)
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
tWR
tRP
DQ
DQS
DM
DI
b
tDQSS (MIN)
DQ
DQS
DM
DI
b
tDQSS (MAX)
DQ
DQS
DM
DI
b
DON’T CARE
TRANSITIONING DATA
tDQSS
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