參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 87/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
88
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams
Figure 49:
Bank Read - Without Auto Precharge
Notes: 1. DOn = data-out from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
detailed DQS and DQ timing.
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS
tIH
tIS
tIH
tIS
tIH
RA
tRCD
tRAS7
tRC
tRP
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ1
DQS
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ1
DQS
tRPRE
tRPST
tDQSCK (MIN)
tDQSCK(MAX)
tLZ (MIN)
tAC (MIN)
tLZ (MIN)
DO
n
tHZ (MAX)
tAC (MAX)
DO
n
NOP6
COMMAND5
3
ACT
RA
Col n
READ2
PRE7
Bank x
RA
Bank x
Bank x4
ACT
Bank x
NOP6
ONE BANK
ALL BANKS
DON’T CARE
TRANSITIONING DATA
x8: A12
x16: A11, A12
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
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