參數(shù)資料
型號(hào)： MT46HC32M16LFCX-75:B
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 7.5 ns, PBGA90
封裝： 9 X 13 MM, GREEN, PLASTIC, VFBGA-90
文件頁數(shù)： 81/98頁
文件大小： 3258K
Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
tDQSS (NOM)
CK
CK#
Command1
WRITE2
NOP
Address
Bank a,
Col b
Bank
(a or all)
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
DQ7
DQS5, 6
DM6
tDQSS (MIN)
DQ7
DQS5, 6
DM6
tDQSS (MAX)
DQ7
DQS5, 6
DM6
tDQSS
Don’t Care
Transitioning Data
DIN
tWR4
PRE3
T4n
T3n
Notes: 1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. DINb = data-in for column b.
512Mb: x16, x32 Mobile LPDDR SDRAM
WRITE Operation
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
82
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
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