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參數(shù)資料
| 型號： | MT46HC32M16LFCX-75:B |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 7.5 ns, PBGA90 |
| 封裝： | 9 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件頁數(shù)： | 32/98頁 |
| 文件大?。?/td> | 3258K |
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Figure 11: READ Command
CS#
WE#
CAS#
RAS#
CKE
Column
Address
A10
BA0, BA1
HIGH
EN AP
DIS AP
Bank
CK
CK#
Don’t Care
Note: 1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The val-
ues on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0]
(where I = the most significant column address bit for each configuration) selects the
starting column location. The value on input A10 determines whether auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the WRITE burst; if auto precharge is not selected, the row will remain open for subse-
quent accesses. Input data appearing on the DQ is written to the memory array, subject
to the DM input logic level appearing coincident with the data. If a given DM signal is
registered LOW, the corresponding data will be written to memory; if the DM signal is
registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
If a WRITE or a READ is in progress, the entire data burst must be complete prior to
stopping the clock (see Clock Change Frequency (page 95)). A burst completion for
WRITEs is defined when the write postamble and tWR or tWTR are satisfied.
512Mb: x16, x32 Mobile LPDDR SDRAM
Commands
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT46V128M4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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