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參數(shù)資料
| 型號(hào)： | MT46HC32M16LFCX-75:B |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 7.5 ns, PBGA90 |
| 封裝： | 9 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件頁(yè)數(shù)： | 52/98頁(yè) |
| 文件大?。?/td> | 3258K |
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Partial-Array Self Refresh
For further power savings during self refresh, the partial-array self refresh (PASR) fea-
ture enables the controller to select the amount of memory to be refreshed during self
refresh. The refresh options include:
Full array: banks 0, 1, 2, and 3
One-half array: banks 0 and 1
One-quarter array: bank 0
One-eighth array: bank 0 with row address most significant bit (MSB) = 0
One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
READ and WRITE commands can still be issued to the full array during standard opera-
tion, but only the selected regions of the array will be refreshed during self refresh. Data
in regions that are not selected will be lost.
Output Drive Strength
Because the device is designed for use in smaller systems that are typically point-to-
point connections, an option to control the drive strength of the output buffers is
provided. Drive strength should be selected based on the expected loading of the mem-
ory bus. The output driver settings are
25Ω, 37Ω, and 55Ω internal impedance for full,
three-quarter, and one-half drive strengths, respectively.
512Mb: x16, x32 Mobile LPDDR SDRAM
Extended Mode Register
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
56
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT46V128M4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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