參數(shù)資料
型號: MPC107
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 8/46頁
文件大?。?/td> 585K
代理商: MPC107
8
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 2 shows the Supply Voltage Sequencing and Separation Cautions.
Figure 2. Supply Voltage Sequencing and Separation Cautions
OVdd/BVdd/GVdd/(LVdd@3.3V - - - -)
Vdd/AVdd/LAVdd
LVdd@5V
Time
3.3V
5V
2.5V
0
6
9
8
8
9
5,7
D
Voltage
Regulator
Delay
Reset
Configuration Pins
HRESET
asserted 255
external memory
clock cycles
3
PLL
Relock
Time
3
100 μs
9 external memory
clock cycles setup time
4
HRESET
Vdd Stable
Power Supply Ramp Up
2
See Note 1 below.
VM = 1.4 V
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
òRecommended Operating Conditionsó.
2. Refer to Paragraph 1.7.2 òPower Supply Voltage Sequencingó for additional information on this topic.
3. Refer to Table 8 for additional information on PLL Relock and reset signal assertion timing requirements.
4. Refer to Table 9. for additional information on reset conTguration pin setup timing requirements.
5. HRESET and HRESET_CPU must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN
clock cycle for the device to be in the non-reset state.
6. HRESET_CPU negates 2
17
memory clock cycles after HRESET negates.
HRESET_CPU
VM = 1.4 V
Maximum rise time must be less than
one external memory clock cycle
6
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