參數(shù)資料
型號(hào)： MPC107
廠商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 28/46頁(yè)
文件大?。?/td> 585K
代理商： MPC107
28
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.3.6 IEEE 1149.1 (JTAG) AC Timing SpeciTcations
Table 16 provides the JTAG AC timing speciTcations for the MPC107 while in the JTAG operating mode.
Notes:
1
2
3
4
TRST is an asynchronous signal. The setup time is for test purposes only.
Non-test (other than TDI and TMS) signal input timing with respect to TCK.
Non-test (other than TDO) signal output timing with respect to TCK.
Timings are independent of the system clock (PCI_SYNC_IN).
Figure 18 shows the JTAG clock input timing diagram.
.
Figure 18. JTAG Clock Input Timing Diagram
Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
At recommended operating conditions (See Figure 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic
4,5
Min
Max
Unit
Notes
TCK Frequency of Operation
0
25
MHz
1
TCK Cycle Time
40
ns
2
TCK Clock Pulse Width Measured at 1.5 V
20
ns
3
TCK Rise and Fall Times
0
3
ns
4
TRST_ Setup Time to TCK Falling Edge
10
ns
1
5
TRST_ Assert Time
10
ns
6
Boundary Scan Input Data Setup Time
5
ns
2
7
Boundary Scan Input Data Hold Time
15
ns
2
8
TCK to Output Data Valid
0
30
ns
3
9
TCK to Output High Impedance
0
30
ns
3
10
TMS, TDI Data Setup Time
5
ns
11
TMS, TDI Data Hold Time
15
ns
12
TCK to TDO Data Valid
0
15
ns
13
TCK to TDO High Impedance
0
15
ns
TCK
2
2
1
VM
VM
VM
3
3
VM = Midpoint Voltage
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